PIC24HJ12GP202-I/SP Microchip Technology, PIC24HJ12GP202-I/SP Datasheet - Page 52

• Manufacturer Part Number: PIC24HJ12GP202-I/SP
• Description: IC PIC MCU FLASH 4KX24 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit or 10-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ12GP201/202
6.1
The PIC24HJ12GP201/202 family of devices have two
types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a BOR. On a cold Reset, the FNOSC configuration
bits in the FOSC device configuration register selects
the device clock source.
A warm Reset is the result of all other Reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>)
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
1.
2.
TABLE 6-1:
DS70282D-page 50
FRC, FRCDIV16,
FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay T
BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
delay T
ensures that the voltage regulator output
becomes stable.
2:
3:
System Reset
DD
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
BOR
LOCK
crosses the V
bits
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
has elapsed. The delay T
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
in
Startup Delay
Oscillator
the
BOR
T
T
T
T
T
T
T
T
POR
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
DD
—
—
OST
threshold and the
Oscillator
crosses the V
has elapsed.
= 32 ms for a 32 kHz crystal.
Control
Oscillator Startup
POR
BOR
Preliminary
Timer
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
3.
4.
5.
6.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power supplies have stabilized at the appropri-
ate level for full-speed operation. After the delay
T
inactive, which enables the selected oscillator to
start generating clock cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 6-1. Refer to Section 8.0
“Oscillator
information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the Reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
elapsed.
PWRT
PLL Lock Time
has elapsed, the SYSRST becomes
T
T
T
T
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
Configuration”
PWRT
© 2009 Microchip Technology Inc.
ensures that the system
T
T
OSCD
OSCD
OST
T
T
T
T
OSCD
Total Delay
= 102.4 μs for a
OSCD
OSCD
OSCD
PWRT
+ T
+ T
T
T
T
OSCD
OSCD
for
LOCK
OST
OST
—
+ T
+ T
+ T
+ T
) after a
LOCK
OST
OST
+ T
+ T
OST
more
FSCM
LOCK
LOCK