PIC18LF45J50-I/ML Microchip Technology, PIC18LF45J50-I/ML Datasheet - Page 6
![IC PIC MCU FLASH 32K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF45J50-I/ML
Manufacturer Part Number
PIC18LF45J50-I/ML
Description
IC PIC MCU FLASH 32K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF45J50-I/ML
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC18F46J50 FAMILY
6. Module: Low-Power Modes (Deep Sleep)
EXAMPLE 2:
DS80436C-page 6
EnterDeepSleep:
Entering Deep Sleep mode takes approximately
2 T
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value registers read synchronization bit
(RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the SLEEP
instruction, but before the Deep Sleep mode has
not been fully entered.
The revision A4 silicon allows insertion of a single
instruction between setting the Deep Sleep Enable
bit (DSEN, DSCONH<7>) and issuing the SLEEP
instruction (see Example 2). The insertion of a NOP
Affected Silicon Revisions
bsf
nop
sleep
(…)
goto
A2
X
CY
, following the SLEEP instruction. Wake-up
A4
DSCONH, DSEN
EnterDeepSleep
DEEP-SLEEP WAKE-UP WORK AROUND
; Enter Deep Sleep mode on SLEEP instruction
; Not compatible with A2 silicon
; Enter Deep Sleep mode
; Add code here to handle wake up events that may
; have been asserted prior to Deep Sleep entry
; re-attempt Deep Sleep entry if desired
instruction before the SLEEP instruction eliminates
the 2 T
missed.
Before using this work around, users should check
their device’s revision ID bits to verify that they
have the A4 silicon. This can be done at run time
by a table read from address, 3FFFFEh.
On revision A2 silicon devices, the instruction can-
not be inserted between setting the DSEN bit and
executing the SLEEP instruction or the device will
enter conventional Sleep mode, not Deep Sleep.
Even on A4 silicon devices, if the firmware imme-
diately executes SLEEP after setting DSEN, the
device will enter Deep Sleep mode without
benefitting from this work around.
CY
window where wake-up events could be
2010 Microchip Technology Inc.