ATMEGA168-20MU Atmel, ATMEGA168-20MU Datasheet

ATMEGA168-20MU

Manufacturer Part Number

ATMEGA168-20MU

Description

IC AVR MCU 16K 20MHZ 32-QFN

Manufacturer

Atmel

Series

AVR® ATmegar

Datasheets

1.ATAVRTS2080B.pdf (378 pages)

2.ATMEGA48-20AU.pdf (35 pages)

3.ATMEGA88-20MU.pdf (33 pages)

Specifications of ATMEGA168-20MU

Core Processor

AVR

Core Size

8-Bit

Speed

20MHz

Connectivity

I²C, SPI, UART/USART

Peripherals

Brown-out Detect/Reset, POR, PWM, WDT

Number Of I /o

Program Memory Size

16KB (8K x 16)

Program Memory Type

FLASH

Eeprom Size

512 x 8

Ram Size

1K x 8

Voltage - Supply (vcc/vdd)

2.7 V ~ 5.5 V

Data Converters

A/D 8x10b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 85°C

Package / Case

32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN

Processor Series

ATMEGA16x

Core

AVR8

Data Bus Width

8 bit

Data Ram Size

1 KB

Interface Type

2-Wire, SPI, USART, Serial

Maximum Clock Frequency

20 MHz

Number Of Programmable I/os

Number Of Timers

Operating Supply Voltage

2.7 V to 5.5 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

3rd Party Development Tools

EWAVR, EWAVR-BL

Development Tools By Supplier

ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT

Minimum Operating Temperature

- 40 C

On-chip Adc

10 bit, 8 Channel

A/d Inputs

8-Channel, 10-Bit

Cpu Speed

20 MIPS

Eeprom Memory

512 Bytes

Input Output

Interface

I2C/SPI/UART/USART

Memory Type

Flash

Number Of Bits

Package Type

32-pin MLF

Programmable Memory

16K Bytes

Timers

2-8-bit, 1-16-bit

Voltage, Range

4.5-5.5 V

Cpu Family

ATmega

Device Core

AVR

Device Core Size

Frequency (max)

20MHz

Total Internal Ram Size

1KB

# I/os (max)

Number Of Timers - General Purpose

Operating Supply Voltage (typ)

3.3/5V

Operating Supply Voltage (max)

5.5V

Operating Supply Voltage (min)

2.7V

Instruction Set Architecture

RISC

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

Controller Family/series

AVR MEGA

No. Of I/o's

Eeprom Memory Size

512Byte

Ram Memory Size

1KB

No. Of Timers

Rohs Compliant

Yes

Package

32MLF EP

Family Name

ATmega

Maximum Speed

20 MHz

For Use With

ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

H&T Electronics

Part Number:

ATMEGA168-20MU

Quantity:

3 000

Current page: 1 of 33
Download datasheet (511Kb)

Features

•

Notes:

High Performance, Low Power AVR

Advanced RISC Architecture

High Endurance Non-volatile Memory segments

Peripheral Features

Special Microcontroller Features

I/O and Packages

Operating Voltage:

Temperature Range:

Speed Grade:

Low Power Consumption

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

– 4/8/16K Bytes of In-System Self-programmable Flash program memory

– 256/512/512 Bytes EEPROM

– 512/1K/1K Bytes Internal SRAM

– Write/Erase cyles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

– Programming Lock for Software Security

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

– 6-channel 10-bit ADC in PDIP Package

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

– 1.8 - 5.5V for ATmega48V/88V/168V

– 2.7 - 5.5V for ATmega48/88/168

– -40

– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

– Active Mode:

– Power-down Mode:

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

250 µA at 1 MHz, 1.8V

15 µA at 32 kHz, 1.8V (including Oscillator)

0.1µA at 1.8V

1. Worst case temperature. Guaranteed after last write cycle.

2. Failure rate less than 1 ppm.

3. Characterized through accelerated tests.

C to 85

8-Bit Microcontroller

C compatible)

(1)(3)

(2)(3)

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

ATmega48/V

ATmega88/V

ATmega168/V

Summary

Rev. 2545LS–AVR–08/07

Related parts for ATMEGA168-20MU

ATMEGA168-20MU Summary of contents

Page 1

... Notes: 1. Worst case temperature. Guaranteed after last write cycle. 2. Failure rate less than 1 ppm. 3. Characterized through accelerated tests. ® 8-Bit Microcontroller (1)(3) (2)( compatible) 8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega48/V ATmega88/V ATmega168/V Summary Rev. 2545LS–AVR–08/07 ...

Page 2

Pin Configurations Figure 1-1. Pinout ATmega48/88/1682545LS TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 ...

Page 3

Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive ...

Page 4

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in 84. 1.1 the supply ...

Page 5

Overview The ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

Page 6

... C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. 2.2 Comparison Between ATmega48, ATmega88, and ATmega168 The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support, and interrupt vector sizes. for the three devices. Table 2-1. ...

Page 7

... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 2545LS–AVR–08/07 ATmega48/88/168 7 ...

Page 8

Register Summary Address Name Bit 7 (0xFF) Reserved – (0xFE) Reserved – (0xFD) Reserved – (0xFC) Reserved – (0xFB) Reserved – (0xFA) Reserved – (0xF9) Reserved – (0xF8) Reserved – (0xF7) Reserved – (0xF6) Reserved – (0xF5) Reserved – ...

Page 9

Address Name Bit 7 (0xBF) Reserved – (0xBE) Reserved – (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved – (0xB6) ASSR – (0xB5) Reserved – (0xB4) OCR2B (0xB3) OCR2A (0xB2) ...

Page 10

Address Name Bit 7 (0x7D) Reserved – (0x7C) ADMUX REFS1 (0x7B) ADCSRB – (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved – (0x76) Reserved – (0x75) Reserved – (0x74) Reserved – (0x73) Reserved – (0x72) Reserved – (0x71) Reserved ...

Page 11

Address Name Bit 7 0x1B (0x3B) PCIFR – 0x1A (0x3A) Reserved – 0x19 (0x39) Reserved – 0x18 (0x38) Reserved – 0x17 (0x37) TIFR2 – 0x16 (0x36) TIFR1 – 0x15 (0x35) TIFR0 – 0x14 (0x34) Reserved – 0x13 (0x33) Reserved – ...

Page 12

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 13

Mnemonics Operands BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical ...

Page 14

... MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break Note: 1. These instructions are only available in ATmega168. ATmega48/88/168 14 Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Flags #Clocks ...

Page 15

... Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive).Also Halide free and fully Green. ...

Page 16

Page 17

... Wide, Plastic Dual Inline Package (PDIP) 2545LS–AVR–08/07 Ordering Code ATmega168V-10AI ATmega168V-10MI ATmega168V-10PI (2) ATmega168V-10AU (2) ATmega168V-10MU (2) ATmega168V-10PU ATmega168-20AI ATmega168-20MI ATmega168-20PI (2) ATmega168-20AU (2) ATmega168-20MU (2) ATmega168-20PU and Figure 27-2 on page 305. Package Type ATmega48/88/168 (1) Package Operational Range 32A 32M1-A 28P3 Industrial ° 32A (-40 ...

Page 18

Packaging Information 7.1 32A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...

Page 19

Pin TOP VIEW 0.20 b BOTTOM VIEW The terminal # Laser-marked Feature. Note: 2325 Orchard Parkway San Jose, CA 95131 R 2545LS–AVR–08/ ...

Page 20

Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 ...

Page 21

A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2545LS–AVR–08/07 ...

Page 22

Errata 8.1 Errata ATmega48 The revision letter in this section refers to the revision of the ATmega48 device. 8.1.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be ...

Page 23

Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. The only safe time to write to any of the Timer2 registers ...

Page 24

necessary to read an EEPROM location after Erase Only, use an Atomic Write opera- tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. ...

Page 25

Errata ATmega88 The revision letter in this section refers to the revision of the ATmega88 device. 8.2.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when ...

Page 26

... Errata ATmega168 The revision letter in this section refers to the revision of the ATmega168 device. 8.3.1 Rev C • ...

Page 27

System Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: - Two succeeding resets are applied where the second reset occurs ...

Page 28

Some parts may get stuck in a reset state when a reset signal is applied when the internal reset state-machine specific state. The internal reset state-machine is in this state for approximately 10 ns immediately before the ...

Page 29

Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 9.1 Rev. 2545L-08/ 9.2 Rev. ...

Page 30

Rev. 2545G-06/ 10. 11. 12. 13. 14. 15. 16. 17 18. 19. 20. 9.7 Rev. 2545F-05/ ATmega48/88/168 30 Updated ...

Page 31

... Updated “Errata ATmega88” on page ATmega48/88/168 22. 33. 35. Table 27-6 on page 309, Table 27-2 on page 90. 291. 303. 349. and “Errata ATmega168” on page 307, Table 25-9 on page 36. 210. 216. 299. “ATmega168” on page 351. and “Errata ATmega168” on page 216. 305. 349. ...

Page 32

Rev. 2545B-01/ 10. 11. 12. ATmega48/88/168 32 Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption Estimates in 34.“Features” on page Updated “Stack Pointer” on page 13 ...

Page 33

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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