PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet - Page 4
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PIC18F87J10-I/PT
Manufacturer Part Number
PIC18F87J10-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F87J10-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DV164136, DM183032, DM164120-5
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
1 837
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F87J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F87J10 FAMILY
11. Module: Enhanced Universal
DS80340B-page 4
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREGx, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• The TXREGx is written to
• The baud rate counter overflows (at the end of
• A Stop bit is transmitted (shifted out of TSR)
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREGx register
when the TRMT bit (TXSTAx<1>) is set, indicating
the TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, load TXREGx immedi-
ately after TXxIF is set or wait 1-bit time after
TXxIF is set. Both solutions prevent writing
TXREGx while a Stop bit is transmitted. Note that
TXxIF is set at the beginning of the Stop bit
transmission.
If transmission is intermittent, do one of the
following:
• Wait for the TRMT bit to be set before loading
• Execute the following:
Date Codes that pertain to this issue:
All engineering and production devices.
the bit period)
TXREGx.
- Use a free timer resource to time the baud
- Set up the timer to overflow at the end of
- Start the timer when you load the TXREGx.
- Do not load the TXREGx when the timer is
period.
Stop bit.
about to overflow.
Synchronous Asynchronous
Receiver Transmitter (EUSART)
12. Module: Enhanced Universal
13. Module: Enhanced Universal
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTAx<0>) is not modified immediately after the
RCIDL bit (BAUDCONx<6>) is set.
Work around
Write to TX9D only when a reception is not in prog-
ress (RCIDL = 1). Since there is no interrupt asso-
ciated with RCIDL, it must be polled in software to
determine when TX9D can be updated.
Date Codes that pertain to this issue:
All engineering and production devices.
After the last received byte has been read from the
EUSART Receive Buffer (RCREGx), the value is
no longer valid for subsequent read operations.
Work around
The RCREGx register should be read only once for
each byte received. After each byte is received from
the EUSART, store the byte into a user variable.
To determine when a byte is available to read from
RCREGx, do one of the following:
• Poll the RCIDL bit (BAUDCONx<6>) for a
• Use the EUSART Receive Interrupt Flag,
Date Codes that pertain to this issue:
All engineering and production devices.
low-to-high transition
RC1IF (PIR1<5>)
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Synchronous Asynchronous
Receiver Transmitter (EUSART)
2010 Microchip Technology Inc.