PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 8

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PIC18F27J13-I/SP

Manufacturer Part Number
PIC18F27J13-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Data Ram Size
3.76 KB
On-chip Adc
Yes
Number Of Programmable I/os
2
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
12 bit
A/d Channels Available
10
Height
3.43 mm
Interface Type
I2C, SPI, USART
Length
34.4 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18F47J13 FAMILY
4. Module:
EXAMPLE 20-2:
DS80503D-page 8
InitSPIPins:
InitMSSP2:
InitSPIDMA:
The code in
MASTER MODE Init AND TRANSFER
set up the PPS registers correctly to map the
SPI2 pins out to the RB<0:2> pins. The cor-
rected code example, with changes in bold, is
shown below.
movlb
bcf
bcf
bcf
bcf
bcf
bsf
movlb
bcf
movlw
movwf
movlw
movwf
bcf
bsf
movlw
movwf
movlw
movwf
movlw
movwf
movlw
movwf
movlb
clrf
movlw
movwf
bsf
movlw
movwf
movlw
movwf
0x0F
EXAMPLE 20-2: 512-BYTE SPI
0x0F
ODCON3, SPI2OD
LATB, RB2
LATB, RB1
TRISB, RB1
TRISB, RB2
TRISB, RB0
0x0E
INTCON, GIE
0x55
EECON2
0xAA
EECON2
PPSCON, IOLOCK
INTCON, GIE
0x03
RPINR21
0x0A
RPOR4
0x0B
RPOR5
0x05
RPINR22
SSP2STAT
b'00000000'
SSP2CON1
SSP2CON1, SSPEN
b'00111010'
DMACON1
b'11110000'
DMACON2
512-BYTE SPI MASTER MODE Init AND TRANSFER
does not
;For this example, let's use RP5(RB2) for SCK2,
;RP4(RB1) for SDO2, and RP3(RB0) for SDI2
;Let's use SPI master mode, CKE = 0, CKP = 0,
;without using slave select signalling.
;Select bank 15, for access to ODCON3 register
;Let's not use open drain outputs in this example
;Initialize our (to be) SCK2 pin low (idle).
;Initialize our (to be) SDO2 pin to a known state
;Make SDO2 output, and drive low
;Make SCK2 output, and drive low (idle state)
;SDI2 is an input, make sure it is tri-stated
;Now we should unlock the PPS registers, so we can
;assign the MSSP2 functions to our desired I/O pins.
;Select bank 14 for access to PPS registers
;I/O Pin unlock sequence will not work if CPU
;services an interrupt during the sequence
;Unlock sequence consists of writing 0x55
;and 0xAA to the EECON2 register.
;We may now write to RPINRx and RPORx registers
;May now turn back on interrupts if desired
;RP3 will be SDI2
;Assign the SDI2 function to pin RP3
;Let's assign SDO2 output to pin RP4
;RPOR4 maps output signals to RP4 pin
;0x0B is SCK2 output
;Assign SCK2 output signal to the RP5 (RB2) pin
;SCK2 needs to be configured as an input on the
;same pin
;SCK2 input function taken from RP5 pin
;Done with PPS registers, bank 15 has other SFRs
;CKE = 0, SMP = 0 (sampled at middle of bit)
;CKP = 0, SPI Master mode, Fosc/4
;MSSP2 initialized
;Enable the MSSP2 module
;Full duplex, RX/TXINC enabled, no SSCON
;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111
;Minimum delay between bytes, interrupt
;only once when the transaction is complete
 2011 Microchip Technology Inc.

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