DSPIC33FJ32GP202-I/MM Microchip Technology, DSPIC33FJ32GP202-I/MM Datasheet - Page 9

• Manufacturer Part Number: DSPIC33FJ32GP202-I/MM
• Description: IC DSPIC MCU/DSP 32K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP202-I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: ECAN, I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

27. Module: QEI
28. Module: QEI
29. Module: SPI
EXAMPLE 2:
© 2010 Microchip Technology Inc.
AD1CON1bits.ADON = 0;
__asm__ volatile ("REPEAT #50");
__asm__ volatile ("NOP");
Sleep();
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
Regardless of the Slave setting for the Frame
delay bit (FRMDLY = 0 or FRMDLY = 1), the Slave
always acts as if the sync pulse precedes the first
SPI data bit (FRMDLY = 0). The SPI will not
function as described if Slave FRMDLY = 1.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
running
A3
A3
X
X
X
A4
A4
A4
X
X
X
the
A5
A5
A5
X
X
X
QEI
in
Timer
//Disable the ADC module
//Wait 50 Tcy
//Repeat NOP 51 times
// Execute PWRSAV #0 and go to Sleep
Gated
30. Module: ADC
Note:
Note:
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around 1:
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in
Affected Silicon Revisions
A2
X
The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Unlike
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
A3
X
PD
) may exceed the specifications listed
A4
X
Work
Example
A5
X
around
2.
PD
DS80461E-page 9
1,
specifications
the
user
#0