PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet

IC PIC MCU FLASH 4KX16 64TQFP

PIC18LF6310-I/PT

Manufacturer Part Number
PIC18LF6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF6310-I/PT

Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm
RoHS Compliant
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
The PIC18F6310/6410/8310/8410 Rev. C0 parts you
have received conform functionally to the Device Data
Sheet
described below. Any Data Sheet Clarification issues
related to the PIC18F6310/6410/8310/8410 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All of the issues listed here will be addressed in future
revisions of the PIC18F6310/6410/8310/8410 silicon.
The
PIC18F6310/6410/8310/8410 devices with these
Device/Revision IDs:
1. Module: Master Synchronous Serial Port
© 2008 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
Part Number
PIC18F6310
PIC18F6410
PIC18F8310
PIC18F8410
Configured in SPI slave mode, the MSSP will gen-
erate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred to the shift register.
Reinitializing the MSSP – by clearing and setting
the SSPEN bit (SSPCON1<5>) prior to rewriting
SSPBUF – will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify that the previous contents have been
transferred by reading the BF bit (SSPSTAT<0>).
If the previous byte has not been transferred:
• Update SSPBUF
• If necessary, clear the WCOL bit
Date Codes that pertain to this issue:
All engineering and production devices.
following
(SSPCON1<7>)
(DS39635B),
PIC18F6310/6410/8310/8410 Rev. C0 Silicon Errata
3FFFFEh:3FFFFFh
(MSSP)
silicon
0000 1011 111
0000 0110 111
0000 1011 110
0000 0110 110
Device ID
except
errata apply
for
in
the
PIC18F6310/6410/8310/8410
Revision ID
the
0 0101
0 0101
0 0101
0 0101
anomalies
only
device’s
to
2. Module: MSSP – Serial Peripheral
3. Module: MSSP – I
In SPI mode, the Buffer Full flag (BF bit in the
SSPSTAT register), the Write Collision Detect bit
(WCOL in SSPCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPCON1 register).
For example, if SSPBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
If if the buffer is full, before disabling the MSSP
module, ensure that:
• SSPBUF is read (thus clearing the BF flag)
• WCOL is clear
If the module is configured in SPI Slave mode,
ensure that the SSPOV bit is clear before disabling
the module.
Date Codes that pertain to this issue:
All engineering and production devices.
In the 10-Bit Slave mode, the I
work correctly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Interface (SPI)
2
C™
2
C™ mode does not
DS80420A-page 1

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PIC18LF6310-I/PT Summary of contents

Page 1

... Update SSPBUF • If necessary, clear the WCOL bit (SSPCON1<7>) Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2. Module: MSSP – Serial Peripheral the anomalies In SPI mode, the Buffer Full flag (BF bit in the ...

Page 2

... Acknowledgement will be received, ACKSTAT = 0 (SSPCON2<7>, even if no slave was addressed on the bus. Work around None. Date Codes that pertain to this issue: the SEN bit All engineering and production devices data and clock © 2008 Microchip Technology Inc. ...

Page 3

... REVISION HISTORY Rev A Document (12/2008) First revision of this document. Includes silicon issues 1 (MSSP) 2 (MSSP – SPI) and 3-5 (MSSP – I © 2008 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C). DS80420A-page 3 ...

Page 4

... PIC18F6310/6410/8310/8410 NOTES: DS80420A-page 4 © 2008 Microchip Technology Inc. ...

Page 5

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 6

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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