PIC24FJ64GA102-I/ML Microchip Technology, PIC24FJ64GA102-I/ML Datasheet - Page 116
PIC24FJ64GA102-I/ML
Manufacturer Part Number
PIC24FJ64GA102-I/ML
Description
IC MCU 16BIT 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
4.PIC24FJ64GA104-IML.pdf
(300 pages)
Specifications of PIC24FJ64GA102-I/ML
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, LIN, SPI, USART
No. Of Pwm Channels
5
Embedded Interface Type
I2C, LIN, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA102-I/ML
Manufacturer:
MAXIM
Quantity:
15 620
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- PIC24FJ64GA104-IML PDF datasheet #4
- Current page: 116 of 308
- Download datasheet (3Mb)
PIC24FJ64GA104 FAMILY
9.2.4.10
V
ing from Deep Sleep functionally looks like a POR, the
technique described in Section 9.2.4.9 “Checking
and Clearing the Status of Deep Sleep” should be
used to distinguish between Deep Sleep and a true
POR event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers, RTCC,
DSWDT, etc.) is reset.
DS39951C-page 116
DD
voltage is monitored to produce PORs. Since exit-
Power-on Resets (
PORs
)
9.2.4.11
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The DSEN bit is automatically cleared.
11. Read and clear the DPSLP status bit in RCON,
12. Read the DSGPRx registers (optional).
13. Once all state related configurations are
14. Application resumes normal operation.
Device exits Reset and begins to execute its
application code.
If DSWDT functionality is required, program the
appropriate Configuration bit.
Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
Enable and configure the RTCC (optional).
Write context data to the DSGPRx registers
(optional).
Enable the INT0 interrupt (optional).
Set the DSEN bit in the DSCON register.
Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
Device exits Deep Sleep when a wake-up event
occurs.
and the DSWAKE status bits.
complete, clear the RELEASE bit.
Summary of Deep Sleep Sequence
2010 Microchip Technology Inc.
Related parts for PIC24FJ64GA102-I/ML
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet: