DSPIC33FJ32MC202-I/SP Microchip Technology, DSPIC33FJ32MC202-I/SP Datasheet - Page 69
![IC DSPIC MCU/DSP 32K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ32MC202-I/SP
Manufacturer Part Number
DSPIC33FJ32MC202-I/SP
Description
IC DSPIC MCU/DSP 32K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
4.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ32MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Package
28SPDIP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC202-I/SP
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
DSPIC33FJ32MC202-I/SP
Manufacturer:
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- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- DSPIC33FJ64MC202-ESO PDF datasheet #4
- Current page: 69 of 320
- Download datasheet (5Mb)
FIGURE 6-3:
6.3
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
register (RCON) is set to indicate the MCLR Reset.
6.3.1
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to Reset the device when
the rest of system is Reset.
6.3.2
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle, and the reset vector fetch
will commence.
© 2011 Microchip Technology Inc.
Section 24.0 “Electrical Characteristics”
SYSRST
SYSRST
SYSRST
External Reset (EXTR)
Software RESET Instruction (SWR)
V
V
V
DD
DD
DD
EXTERNAL SUPERVISORY CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
V
DD
dips before PWRT expires
BROWN-OUT SITUATIONS
DD
. In this case, the
for
T
BOR
+ T
T
T
PWRT
BOR
BOR
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.5
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate
the
“Watchdog Timer (WDT)”
Watchdog Reset.
6.6
If
higher-priority trap is being processed, a hard trap
conflict Reset occurs. The hard traps include
exceptions of priority level 13 through level 15,
inclusive. The address error (level 13) and oscillator
error (level 14) traps fall into this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to
more information on trap conflict Resets.
+ T
+ T
a
PWRT
PWRT
Watchdog
lower-priority
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
Section 7.0 “Interrupt Controller”
Reset.
hard
Refer
V
V
for more information on
V
trap
BOR
BOR
BOR
occurs
DS70283H-page 69
to
Section 21.4
while
for
a
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