PIC16F84A-04/P Microchip Technology, PIC16F84A-04/P Datasheet - Page 294
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84A-04/P
Manufacturer Part Number
PIC16F84A-04/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84A-04/P
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84A-04/P
Manufacturer:
MICROCHIP
Quantity:
1 450
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PICmicro MID-RANGE MCU FAMILY
17.4
DS31017A-page 17-18
SSP I
2
C™ Operation
The MSSP module in I
eral call support) and provides interrupts on start and stop bits in hardware to determine a free
bus (multi-master function). The SSP module implements the standard mode specifications as
well as 7-bit and 10-bit addressing.
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 17-10: I
Figure 17-11: I
2
2
C Slave Mode Block Diagram
C Master Mode Block Diagram
SDA
SDA
SCL
Baud Rate Generator
2
SCL
SSPADD<6:0>
C mode fully implements all master and slave functions (including gen-
Preliminary
7
Read
Read
Appendix A
clock
clock
shift
shift
MSb
MSb
Start and Stop bit
detect / generate
Stop bit detect
Match detect
SSPBUF reg
Match detect
SSPADD reg
SSPBUF reg
SSPADD reg
SSPSR reg
SSPSR reg
Start and
gives an overview of the I
LSb
LSb
Write
Write
data bus
data bus
Internal
Internal
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
Address Match
Address Match
Set, Reset
S, P bits
and
1997 Microchip Technology Inc.
2
C bus specification.
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