PIC24FJ64GA004-E/PT Microchip Technology, PIC24FJ64GA004-E/PT Datasheet
PIC24FJ64GA004-E/PT
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PIC24FJ64GA004-E/PT Summary of contents
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... Revision ID value appear in the Output window. If you are unable to extract the silicon Note: revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC24FJ64GA004 family silicon revisions are shown in Revision ID for Silicon Revision (1) Device ID ...
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... PIC24FJ64GA004 FAMILY TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number JTAG — 1. LVD — 2. Core Idle mode 3. Core Doze mode 4. Core BOR 5. Core RAM 6. A/D — 7. A/D — 8. A/D — SDA Line 10. State (I2C1) UART — 11. UART — 12. UART Auto-Baud 13. ...
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... A/D — 51. Converter Only those issues indicated in the last column apply to the current silicon revision. Note 1: 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Issue Summary PERR and FERR not correctly set for all bytes in receive FIFO. Spontaneous BOR events with low-range V . ...
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... PIC24FJ64GA004 FAMILY Silicon Errata Issues This document summarizes all silicon Note: errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B8). 1. Module: JTAG When the JTAG is disabled, the pull-up resistor on the TDI pin (pin 35/RA9) will stay enabled on the 44-pin variants of the device ...
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... ADC to reference channels AN16-31. Affected Silicon Revisions A3 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 8. Module: A/D The A/D module will not generate code 511. Any conversion which should result in 511 normally, will instead generate 510 or 512. Work around None. Affected Silicon Revisions A3/ ...
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... PIC24FJ64GA004 FAMILY 2 10. Module: I C™ (I2C1, SDA Line State) When using I2C1, the SDA1 line state may not be detected properly unless it is first held low for 2 150 ns after enabling the I C module. In Master mode, this error may cause a bus colli- sion to occur instead of a Start bit transmission ...
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... 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 17. Module: Output Compare In PWM mode, the output compare module may miss a compare event when the current duty cycle register (OCxRS) value is 0x0000 (0% duty cycle) and the OCxRS register is updated with a value of 0x0001. The compare event is only missed the first time a value of 0x0001 is written to OCxRS and the PWM output remains low for one PWM period ...
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... PIC24FJ64GA004 FAMILY 19. Module: SPI In SPI Slave mode (MSTEN = 0), with the slave select option enabled (SSEN = 1), the peripheral may accept transfers regardless of the SSx pin state. The received data in SPIxBUF will be accurate but not intended for the device. Work around There is a work around using the Peripheral Pin Select (PPS) feature ...
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... All I/O Pins Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only Note 1: and are not tested. 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY , meet the OH Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) -40°C T ...
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... PIC24FJ64GA004 FAMILY 22. Module: I/O Ports During Power-on Reset (POR), the device may drive the OSCO/RA3 pin as a clock out output for approximately 20 S. During this time, the pin will be driven high and low rather than being set to high-impedance. This may cause issues on designs that use the pin as a general purpose I/O ...
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... A3 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 28. Module: I/O (Peripheral Pin Select) The remappable pin functions multiplexed to some pins do not have a higher priority than fixed digital signals assigned to those pins. By design, a remapped digital function should always have operation priority over any other fixed digital function on the same pin ...
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... PIC24FJ64GA004 FAMILY 30. Module: UART (FIFO Error Flags) Under certain circumstances, the PERR and FERR error bits may not be correct for all bytes in the receive FIFO. This has only been observed when both of the following conditions are met: • the UART receive interrupt is set to occur when the FIFO is full or 3/4 full (UxSTA< ...
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... EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK while(IFS0bits.SPI1IF == 0){} while(PORTDbits.RD1 == 1){} SPI1BUF = 0xFF; 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 36. Module (Master Mode) Under certain circumstances, a module operating in Master mode may Acknowledge its own com- mand addressed to a slave device. This happens when the following occurs: • ...
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... PIC24FJ64GA004 FAMILY 2 37. Module (Slave Mode) Under certain circumstances, a module operating in Slave mode may not respond correctly to some of the special addresses reserved by the I This happens when the following occurs: • 10-Bit Addressing mode is used (A10M = 1); and • bits, A<7:1>, of the slave address (I2CADD< ...
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... A3 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 45. Module: Core Operations that immediately follow any manipula- tions of the DOZE<2:0> or DOZEN bits (CLKDIV<14:11>) may not execute properly. In particular, for instructions that operate on an SFR, data may not be read properly. Also, bits automatically cleared in hardware may not be cleared if the operation occurs during this interval ...
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... PIC24FJ64GA004 FAMILY 47. Module: SPI (Master Mode) When operating in Enhanced Buffer Master mode, the Transmit Buffer Full flag, SPITBF, may be cleared before all data in the FIFO buffer has actually been sent. This may result in data being overwritten before it can be sent. This has only been observed when the SPI clock prescalers are configured for a divider of greater than 1:4 ...
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... Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When the regulator is enabled, a low-ESR (< 5Ω) capacitor is required on the V stabilize the voltage regulator output voltage. The V V pin must not be connected to V DDCORE use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum ...
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... PIC24FJ64GA004 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. ...
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... Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only Note 1: and are not tested. This is the limit to which 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 27-3. The Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature-40°C < -40°C < T (1) ...
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... This document replaces these errata documents: • “PIC24FJ64GA004 Family Revision A3 Silicon Errata” (DS80316) • “PIC24FJ64GA004 Family Revision B4 Silicon Errata” (DS80384) • “PIC24FJ64GA004 Family Data Sheet Errata” (DS80333) DS80470E-page 20 Rev B Document (7/2009) Amended existing silicon revision A3 as joint revision A3/A4 ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. 08/04/10 ...