PIC16F84A-04/SO Microchip Technology, PIC16F84A-04/SO Datasheet - Page 324

• Manufacturer Part Number: PIC16F84A-04/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-04/SO

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F84A - BOARD DAUGHTER ICEPIC3309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
17.4.15
17.4.16
17.4.17
DS31017A-page 17-48
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
Clock Arbitration
Sleep Operation
Effect of a Reset
Clock arbitration occurs when the master, during any receive, transmit, or Repeated Start/stop
condition de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float
high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always
be at least one BRG rollover count in the event that the clock is held low by an external device
(Figure
Figure 17-33: Clock Arbitration Timing in Master Transmit Mode
While in sleep mode, the I
or complete byte transfer occurs wake the processor from sleep (if the MSSP interrupt is
enabled).
A reset disables the MSSP module and terminates the current transfer.
T
17-33).
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
2
C module can receive addresses or data, and when an address match
Preliminary
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
T
SCL = 1 BRG starts counting
clock high interval.
BRG
1997 Microchip Technology Inc.
osc
4).