PIC24FJ64GA104-I/ML Microchip Technology, PIC24FJ64GA104-I/ML Datasheet - Page 14
![IC PIC MCU FLASH 64KB 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ64GA104-I/ML
Manufacturer Part Number
PIC24FJ64GA104-I/ML
Description
IC PIC MCU FLASH 64KB 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA180025.pdf
(12 pages)
2.PIC24FJ32GA102-ISP.pdf
(308 pages)
3.PIC24FJ32GA102-ISP.pdf
(12 pages)
4.PIC24FJ32GA102-ISP.pdf
(48 pages)
5.PIC24FJ64GA104-IPT.pdf
(36 pages)
6.PIC24FJ64GA104-IML.pdf
(300 pages)
Specifications of PIC24FJ64GA104-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
44-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001, MA240020, DM240002, DM240011, DV164033
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA104-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 200
PIC24FJ64GA1/GB0
TABLE 3-4:
DS39934B-page 14
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to erase all program memory.
Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.
Step 4: Initiate the erase cycle.
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0000
SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
000000
040200
000000
2404FA
883B0A
2xxxx0
880190
200000
BB0800
000000
000000
A8E761
000000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
(Hex)
Data
NOP
GOTO
NOP
MOV
MOV
MOV
MOV
MOV
TBLWTL
NOP
NOP
BSET
NOP
NOP
GOTO
NOP
MOV
MOV
NOP
Clock out contents of the VISI register.
NOP
0x200
#0x404F, W10
W10, NVMCON
#<PAGEVAL>, W0
W0, TBLPAG
#0x0000, W0
W0,[W0]
NVMCON, #WR
0x200
NVMCON, W2
W2, VISI
Description
© 2009 Microchip Technology Inc.