PIC18F87J90-I/PT Microchip Technology, PIC18F87J90-I/PT Datasheet - Page 2
PIC18F87J90-I/PT
Manufacturer Part Number
PIC18F87J90-I/PT
Description
IC PIC MCU FLASH 128KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F67J90-IPT.pdf
(450 pages)
2.PIC18F67J90-IPT.pdf
(3 pages)
3.PIC18F67J90-IPT.pdf
(10 pages)
4.PIC18F66J90-IPT.pdf
(444 pages)
Specifications of PIC18F87J90-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J90-I/PT
Manufacturer:
MICROCHIP
Quantity:
4 000
Company:
Part Number:
PIC18F87J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J90 FAMILY
TABLE 2:
DS80432E-page 2
MSSP
EUSART
RTCC
RTCC
MSSP
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
I
Enable/
Disable
INTRC
Clock
Port
Override
I
2
2
C™ Slave
C Mode
Feature
SILICON ISSUE SUMMARY
Number
Item
1.
2.
3.
4.
5.
If the SSPBUF register is not read within a
window after the SSPIF interrupt, the
module may not receive the correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
delay.
The INTRC clock is not automatically
enabled when it is selected.
The RTCC output does not override the
associated TRIS bit.
If a Stop condition occurs in the middle of an
address or data reception, there will be
issues with the SCL clock stream and RCEN
bit.
Issue Summary
CY
2010 Microchip Technology Inc.
A1
X
X
X
X
X
Affected Revisions
A3
X
X
X
(1)