PIC16F84A-20/P Microchip Technology, PIC16F84A-20/P Datasheet - Page 661

• Manufacturer Part Number: PIC16F84A-20/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-20/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.4.2
Parameter
Microchip
1997 Microchip Technology Inc.
SCL
SDA
No.
90
91
92
93
Clock Synchronization
T
T
T
T
SU
HD
SU
HD
Sym
:
:
:
:
STA
STO
STA
STO
90
Clock synchronization occurs after the devices have started arbitration. This is performed using
a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the con-
cerned devices to start counting off their low period. Once a device clock has gone low, it will hold
the SCL line low until its SCL high state is reached. The low to high transition of this clock may
not change the state of the SCL line, if another device clock is still within its low period. The SCL
line is held low by the device with the longest low period. Devices with shorter low periods enter
a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start
counting off their high periods. The first device to complete its high period will pull the SCL line
low. The SCL line high time is determined by the device with the shortest high period,
Figure
Figure A-10:
Figure A-11:
Table A-2:
Condition
START
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
A-10.
91
Characteristic
Clock Synchronization
I
I
2
2
C Bus Start/Stop Bits Timing Specification
C Bus Start/Stop Bits Timing Specification
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
SCL
CLK
CLK
1
2
4700
4000
4700
4000
Min
600
600
600
600
counter
reset
state
wait
Typ
—
—
—
—
—
—
—
—
Max
start counting
HIGH period
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
Appendix A
92
Condition
STOP
Only relevant for
repeated START condi-
tion
After this period the first
clock pulse is generated
93
DS31034A-page 34-9
Conditions
34