PIC16C55-HSI/SO Microchip Technology, PIC16C55-HSI/SO Datasheet - Page 49
![IC MCU OTP 512X12 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16C55-HSI/SO
Manufacturer Part Number
PIC16C55-HSI/SO
Description
IC MCU OTP 512X12 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16LC58B-04P.pdf
(194 pages)
Specifications of PIC16C55-HSI/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
20
Program Memory Size
768B (512 x 12)
Program Memory Type
OTP
Ram Size
24 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164002 - MODULE SKT PROMATEII 18/28SOIC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
Connectivity
-
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9.3
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
9.3.1
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/V
For lowest current consumption while powered down,
the T0CKI input should be at V
MCLR/V
(MCLR = V
9.3.2
The device can wake up from SLEEP through one of
the following events:
1.
2.
Both of these events cause a device RESET. The TO
and PD bits can be used to determine the cause of
device RESET. The TO bit is cleared if a WDT time-
out occurred (and caused wake-up). The PD bit, which
is set on power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
2002 Microchip Technology Inc.
An external RESET input on MCLR/V
A Watchdog Timer Time-out Reset (if WDT was
enabled).
PP
Power-Down Mode (SLEEP)
IH
pin must be at a logic high level
SLEEP
WAKE-UP FROM SLEEP
).
DD
PP
or V
pin low.
PP
SS
pin.
and the
Preliminary
9.4
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
9.5
Four memory locations are designated as ID locations
where the user can store checksum or other code-iden-
tification numbers. These locations are not accessible
during normal execution but are readable and writable
during program/verify.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ’1’s.
Note:
Note:
Program Verification/Code
Protection
ID Locations
Microchip does not recommend code pro-
tecting windowed devices.
Microchip will assign a unique pattern
number for QTP and SQTP requests and
for ROM devices. This pattern number will
be unique and traceable to the submitted
code.
PIC16C5X
DS30453D-page 47
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