PIC16LF84A-04I/SO Microchip Technology, PIC16LF84A-04I/SO Datasheet - Page 28

• Manufacturer Part Number: PIC16LF84A-04I/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF84A-04I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 20MHz
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F8X
FIGURE 6-3:
FIGURE 6-4:
DS30430C-page 28
PC
Instruction
TMR0
Instruction
Execute
Fetch
INSTRUCTION FLOW
GIE bit
(INTCON<7>)
T0IF bit
(INTCON<2>)
Instruction
fetched
TMR0 timer
Instruction
executed
CLKOUT
OSC1
4
PC
(3)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: T0IF interrupt flag is sampled here (every Q1).
T0
PC-1
Q1
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TMR0 INTERRUPT TIMING
The TMR0 register will roll over 3 Tosc cycles later.
FEh
Inst (PC)
Inst (PC-1)
Q2
1
PC
MOVWF TMR0
Q3
PC
T0+1
Q4
Q1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
FFh
Write TMR0
executed
Inst (PC+1)
PC+1
Inst (PC)
Q2
1
PC +1
Q3
Read TMR0
reads NT0
Q4
PC+2
Q1
Interrupt Latency
00h
Dummy cycle
Q2
PC +1
Read TMR0
reads NT0
PC+3
Q3
NT0
(2)
Q4
MOVF TMR0,W
Read TMR0
reads NT0
Q1
PC+4
01h
Dummy cycle
Inst (0004h)
Q2
0004h
Q3
MOVF TMR0,W
Read TMR0
reads NT0
1998 Microchip Technology Inc.
PC+5
Q4
Q1
02h
Read TMR0
reads NT0 + 1
Inst (0004h)
Inst (0005h)
NT0+1
Q2
0005h
PC+6
Q3
Q4