DSPIC33FJ64GP204-I/ML Microchip Technology, DSPIC33FJ64GP204-I/ML Datasheet - Page 50
![IC DSPIC MCU/DSP 64K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ64GP204-I/ML
Manufacturer Part Number
DSPIC33FJ64GP204-I/ML
Description
IC DSPIC MCU/DSP 64K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP204-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
ECAN, I2C, JTAG, SPI, UART
No. Of I/o's
35
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 50 of 412
- Download datasheet (6Mb)
TABLE 4-10:
TABLE 4-11:
TABLE 4-12:
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
SFR Name
SFR Name
SFR Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
SFR
0230
0232
0234
0236
0238
Addr
Addr
SFR
0240
0242
0244
0248
SFR
0260
0262
0264
0268
UART2 REGISTER MAP
SPI1 REGISTER MAP
SPI2 REGISTER MAP
UTXISEL1
UARTEN
FRMEN
FRMEN
Bit 15
Bit 15
SPIEN
Bit 15
SPIEN
—
—
—
—
UTXINV
Bit 14
SPIFSD
SPIFSD
Bit 14
Bit 14
—
—
—
—
—
—
—
UTXISEL0
Bit 13
USIDL
FRMPOL
FRMPOL
SPISIDL
SPISIDL
—
—
Bit 13
Bit 13
—
—
Bit 12
IREN
DISSCK
DISSCK
—
—
—
Bit 12
Bit 12
—
—
—
—
UTXBRK
RTSMD
Bit 11
DISSDO
DISSDO
Bit 11
Bit 11
—
—
—
—
—
—
UTXEN
Bit 10
MODE16
MODE16
Bit 10
Bit 10
—
—
—
—
—
—
—
UTXBF
UEN1
Bit 9
SPI1 Transmit and Receive Buffer Register
SPI2 Transmit and Receive Buffer Register
—
—
Bit 9
SMP
Bit 9
SMP
—
—
—
—
Baud Rate Generator Prescaler
TRMT
UEN0
UTX8
URX8
Bit 8
Bit 8
Bit 8
CKE
CKE
—
—
—
—
WAKE
Bit 7
URXISEL<1:0>
SSEN
SSEN
Bit 7
Bit 7
—
—
—
—
LPBACK
SPIROV
SPIROV
Bit 6
Bit 6
Bit 6
CKP
CKP
—
—
ABAUD
ADDEN
MSTEN
MSTEN
Bit 5
Bit 5
Bit 5
—
—
—
—
UART Transmit Register
UART Receive Register
URXINV
RIDLE
Bit 4
Bit 4
Bit 4
—
—
—
—
SPRE<2:0>
SPRE<2:0>
BRGH
PERR
Bit 3
Bit 3
Bit 3
—
—
—
—
FERR
Bit 2
Bit 2
Bit 2
PDSEL<1:0>
—
—
—
—
FRMDLY
FRMDLY
OERR
SPITBF
SPITBF
Bit 1
Bit 1
Bit 1
PPRE<1:0>
PPRE<1:0>
URXDA
STSEL
SPIRBF
SPIRBF
Bit 0
Bit 0
Bit 0
—
—
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
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