PIC32MX420F032H-40I/MR Microchip Technology, PIC32MX420F032H-40I/MR Datasheet - Page 75

IC PIC MCU FLASH 32KX32 64-QFN

PIC32MX420F032H-40I/MR

Manufacturer Part Number
PIC32MX420F032H-40I/MR
Description
IC PIC MCU FLASH 32KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX420F032H-40I/MR

Core Size
32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
MIPS32® M4K™
Speed
40MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
13.0
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Low-Power Secondary
Oscillator (SOSC) for real-time clock applications. The
following modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
FIGURE 13-1:
© 2009 Microchip Technology Inc.
Note:
SOSCO/T1CK
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
SOSCI
TIMER1
T1IF
Event Flag
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
reference source. Refer to the “PIC32MX
Family Reference Manual” Section 14.
“Timers” (DS61105)
description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Configuration Word DEVCFG1.
TGATE (T1CON<7>)
TIMER1 BLOCK DIAGRAM
0
1
Reset
Equal
SOSCEN
for
16-bit Comparator
a
TMR1
PR1
detailed
Preliminary
PBCLK
Q
Q
(1)
Gate
Sync
D
13.1
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
• Asynchronous mode can be used with the SOSC
registers
to function as a Real-Time Clock (RTC).
PIC32MX3XX/4XX
Additional Supported Features
1 0
x 1
0 0
TSYNC (T1CON<2>)
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
0
1
1, 8, 64, 256
(T1CON<5:4>)
Prescaler
TCKPS<1:0>
Sync
DS61143F-page 73
2

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