DSPIC33FJ128MC202-I/SO Microchip Technology, DSPIC33FJ128MC202-I/SO Datasheet - Page 4

IC DSPIC MCU/DSP 128K 28SOIC

DSPIC33FJ128MC202-I/SO

Manufacturer Part Number
DSPIC33FJ128MC202-I/SO
Description
IC DSPIC MCU/DSP 128K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC202-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
System Management:
• Flexible clock options:
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
Audio Digital-to-Analog Converter (DAC):
Comparator Module:
• Two analog comparators with programmable
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
DS70291E-page 4
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
- Two and four simultaneous samples (10-bit ADC)
- Up to nine input channels with auto-scanning
- Conversion start can be manual or
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
- 16-bit Dual Channel DAC module
- 100 Ksps maximum sampling rate
- Second-Order Digital Delta-Sigma Modulator
input/output configuration
synchronized with one of four trigger sources
Motor Control Peripherals:
• 6-channel 16-bit Motor Control PWM:
• 2-channel 16-bit Motor Control PWM:
• 2-Quadrature Encoder Interface module:
- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead-time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
- PWM frequency for 11-bit resolution
- One duty cycle generator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
- PWM frequency for 11-bit resolution
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
© 2011 Microchip Technology Inc.

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