DSPIC33FJ128MC202-I/SO Microchip Technology, DSPIC33FJ128MC202-I/SO Datasheet - Page 7
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DSPIC33FJ128MC202-I/SO
Manufacturer Part Number
DSPIC33FJ128MC202-I/SO
Description
IC DSPIC MCU/DSP 128K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC202-I/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
17. Module: ECAN
18. Module: CPU
© 2010 Microchip Technology Inc.
The ECAN module may not store received data in
the correct location. When this occurs, the receive
buffers will become corrupted. In addition, it is also
possible for the transmit buffers to become
corrupted. This issue is more likely to occur as the
CAN bus speed approaches 1 Mbps.
Work around
Do not use the DMA with ECAN in Peripheral
Indirect mode. Use the DMA in Register Indirect
mode, Continuous mode enabled and Ping Pong
mode disabled. The receive DMA channel count
should be set to 8 words. The transmit DMA
channel count should be set for the actual
message size (maximum of 7 words for Extended
CAN messages and 6 words for Standard CAN
Messages). To simplify application error handling
while using this mode, only one TX buffer should
be used. While message filtering is not affected,
messages will not be stored at distinct RX buffers.
Instead all messages are stored contiguously in
memory. The start of this memory is pointed to by
the receive DMA channel. The application must
still clear RXFUL flags and other interrupt flags.
The application must manage the RX buffer
memory.
Affected Silicon Revisions
The EXCH instruction does not execute correctly.
Work around
If
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
A1
A1
X
X
writing
A2
A2
X
X
source
A3
A3
X
X
A4
A4
X
code
in
assembly,
the
19. Module: PWM
20. Module: PWM
21. Module: SPI
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up, as if PTDIR was zero.
Work around
None.
Affected Silicon Revisions
When the device is operated in DOZE mode and
the Motor Control PWM module has a postscaler
set to any value different than 1:1 (PTOPS > 0 in
PxTCON register), the Motor Control PWM
module generates more interrupts than expected.
Work around
Do not use DOZE mode with the Motor Control
PWM if the time base output postscaler is different
than 1:1 (PTOPS > 0 in PxTCON register).
Affected Silicon Revisions
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data. Applications which use SPI
with DMA will not be affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI Clock before writing to the
SPIxBUF register.
Alternatively, do one of the following:
1. Poll the RBF bit and wait for it to get set before
2. Poll the SPI Interrupt flag and wait for it to get
3. Use an SPI Interrupt Service Routine.
4. Use DMA.
Affected Silicon Revisions
A1
A1
A1
X
X
X
writing to the SPIxBUF register.
set before writing to the SPIxBUF register.
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
DS80442F-page 7