PIC16F84-04I/P Microchip Technology, PIC16F84-04I/P Datasheet - Page 346
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04I/P
Manufacturer Part Number
PIC16F84-04I/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 346 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
Figure 18-3:
Table 18-6: Registers Associated with Asynchronous Transmission
DS31018A-page 18-10
PIR
RCSTA
TXREG
PIE
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'.
Note 1: The position of this bit is device dependent.
Name
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Write to TXREG
BRG output
(shift clock)
TX/CK pin
Shaded cells are not used for Asynchronous Transmission.
CSRC
SPEN
Bit 7
TX7
Asynchronous Master Transmission (Back to Back)
Note: This timing diagram shows two consecutive transmissions.
Bit 6
RX9
TX6
TX9
Transmit Shift Reg.
WORD 1
Word 1
SREN
TXEN
Bit 5
TX5
Start Bit
Word 2
CREN
SYNC
Bit 4
TX4
TXIE
TXIF
Bit 0
(1)
Bit 3
(1)
TX3
—
—
Bit 1
BRGH
FERR
WORD 1
Bit 2
TX2
OERR
TRMT
Bit 1
TX1
Bit 7/8
RX9D
TX9D
Bit 0
TX0
WORD 2
Transmit Shift Reg.
Stop Bit
1997 Microchip Technology Inc.
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
0
0
Start Bit
WORD 2
0000 -00x
0000 0000
0000 -010
0000 0000
Value on
all other
Resets
0
0
Bit 0
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