DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 177

• Manufacturer Part Number: DSPIC33FJ128GP306A-I/PT
• Description: IC DSPIC MCU/DSP 128K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP306A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 18-chx10-bit|18-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The
support up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• Simple Capture Event modes:
FIGURE 14-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the fea-
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
input at ICx pin
input at ICx pin
dsPIC33FJXXXGPX06A/X08A/X10A
2: Some registers and associated bits
INPUT CAPTURE
tures of the dsPIC33FJXXXGPX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive
complement the information in this data
sheet, refer to Section 12. “Input
Capture” (DS70198) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Prescaler
(1, 4, 16)
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
reference
ICM<2:0> (ICxCON<2:0>)
dsPIC33FJXXXGPX06A/X08A/X10A
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Edge Detection Logic
source.
Clock Synchronizer
ICxI<1:0>
and
devices
To
in
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
• Capture timer value on every edge (rising and fall-
• Prescaler Capture Event modes:
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or exter-
nal clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Input capture can also be used to provide
ing)
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
additional sources of external interrupts
Note:
- Capture timer value on every 4th rising
- Capture timer value on every 16th rising
4 buffer locations are filled
edge of input at ICx pin
edge of input at ICx pin
Logic
FIFO
R/W
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to 1 (ICI<1:0> = 00).
From 16-bit Timers
TMRy TMRz
1
ICxBUF
16
0
DS70593C-page 177
16
ICTMR
(ICxCON<7>)