PIC18LF4331-I/P Microchip Technology, PIC18LF4331-I/P Datasheet - Page 169
![IC PIC MCU FLASH 4KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4331-I/P
Manufacturer Part Number
PIC18LF4331-I/P
Description
IC PIC MCU FLASH 4KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
9.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18LF4331-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF4331-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18LF4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- PIC18F4331-EP PDF datasheet #9
- Current page: 169 of 392
- Download datasheet (4Mb)
17.3
The Motion Feedback Module includes three noise
rejection
RA3/AN3/V
The filter block also includes a fourth filter for the T5CKI
pin. They are intended to help reduce spurious noise
spikes which may cause the input signals to become
corrupted at the inputs. The filter ensures that the input
signals are not permitted to change until a stable value
has been registered for three consecutive sampling
clock cycles.
The filters are controlled using the Digital Filter Control
(DFLTCON) register (see
can be individually enabled or disabled by setting or
clearing the corresponding FLTxEN bit in the
DFLTCON register. The sampling frequency, which
must be the same for all three noise filters, can be
REGISTER 17-3:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Note:
U-0
—
Noise Filters
REF
filters
The noise filter output enables are functional in both QEI and IC Operating modes.
The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering.
Unimplemented: Read as ‘0’
FLT4EN: Noise Filter Output Enable bit (T5CKI input)
1 = Enabled
0 = Disabled
FLT3EN: Noise Filter Output Enable bit (CAP3/QEB input)
1 = Enabled
0 = Disabled
FLT2EN: Noise Filter Output Enable bit (CAP2/QEA input)
1 = Enabled
0 = Disabled
FLT1EN: Noise Filter Output Enable bit (CAP1/INDX Input)
1 = Enabled
0 = Disabled
FLTCK<2:0>: Noise Filter Clock Divider Ratio bits
111 = Unused
110 = 1:128
101 = 1:64
100 = 1:32
011 = 1:16
010 = 1:4
001 = 1:2
000 = 1:1
+/CAP2/QEA and RA4/AN4/CAP3/QEB.
FLT4EN
R/W-0
on
DFLTCON: DIGITAL FILTER CONTROL REGISTER
RA2/AN2/V
Register
W = Writable bit
‘1’ = Bit is set
FLT3EN
R/W-0
17-3). The filters
REF
(1)
-/CAP1/INDX,
PIC18F2331/2431/4331/4431
FLT2EN
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLT1EN
R/W-0
programmed by the FLTCK<2:0> Configuration bits.
T
block.
The noise filters can either be added or removed from
the input capture, or QEI signal path, by setting or
clearing the appropriate FLTxEN bit, respectively. Each
capture channel provides for individual enable control
of the filter output. The FLT4EN bit enables or disables
the noise filter available on the T5CKI input in the
Timer5 module.
The filter network for all channels is disabled on
Power-on and Brown-out Resets, as the DFLTCON
register is cleared on Resets. The operation of the filter
is shown in the timing diagram in
CY
is used as the clock reference to the clock divider
(1)
(1)
(1)
(1)
FLTCK2
R/W-0
x = Bit is unknown
FLTCK1
R/W-0
Figure
DS39616D-page 169
17-14.
FLTCK0
R/W-0
bit 0
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