DSPIC33FJ64MC506A-I/PT Microchip Technology, DSPIC33FJ64MC506A-I/PT Datasheet - Page 164
![IC DSPIC MCU/DSP 64K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ64MC506A-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506A-I/PT
Description
IC DSPIC MCU/DSP 64K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC506A-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
53
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33FJXXXMCX06A/X08A/X10A
11.2
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
See “Pin Diagrams” for the available pins and their
functionality.
11.3
The ADxPCFGH, ADxPCFGL and TRIS registers control
the operation of the ADC port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bit set (input). If the TRIS bit is cleared (output), the
digital output level (V
Clearing any bit in the ADxPCFGH or ADxPCFGL reg-
ister configures the corresponding bit to be an analog
pin. This is also the Reset state of any I/O pin that has
an analog (ANx) function associated with it.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EXAMPLE 11-1:
DS70594B-page 164
Note:
Note:
MOV
MOV
NOP
btss
Open-Drain Configuration
Configuring Analog Port Pins
In devices with two ADC modules, if the
corresponding
AD1PCFGH(L) and AD2PCFGH(L) is
cleared, the pin is configured as an analog
input.
The voltage on an analog input pin can be
between -0.3V to (V
0xFF00, W0
W0, TRISBB
PORTB, #13
IH
specification.
OH
DD
PORT WRITE/READ EXAMPLE
or V
(e.g., 5V) on any desired 5V
OL
PCFG
) is converted.
DD
+ 0.3 V).
bit
in
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
either
Preliminary
11.4
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.5
The input change notification function of the I/O ports
allows
devices to generate interrupt requests to the processor
in response to a change-of-state on selected input pins.
This
change-of-states even in Sleep mode, when the clocks
are disabled. Depending on the device pin count, there
are up to 24 external signals (CN0 through CN23) that
can be selected (enabled) for generating an interrupt
request on a change-of-state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
CN Interrupt Enable (CNxIE) control bits for each of the
CN input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the Weak Pull-up
Enable (CNxPUE) bits for each of the CN pins. Setting
any of the control bits enables the weak pull-ups for the
corresponding pins.
Note:
feature
I/O Port Write/Read Timing
Input Change Notification
the
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
is
dsPIC33FJXXXMCX06A/X08A/X10A
capable
2009 Microchip Technology Inc.
of
detecting
input
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