ATMEGA16-16AU Atmel, ATMEGA16-16AU Datasheet

IC AVR MCU 16K 16MHZ 5V 44TQFP

ATMEGA16-16AU

Manufacturer Part Number
ATMEGA16-16AU
Description
IC AVR MCU 16K 16MHZ 5V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– 2.7V - 5.5V for ATmega16L
– 4.5V - 5.5V for ATmega16
– 0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
True Read-While-Write Operation
Mode
and Extended Standby
In-System Programming by On-chip Boot Program
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16
ATmega16L
Summary
Rev. 2466TS–AVR–07/10

Related parts for ATMEGA16-16AU

ATMEGA16-16AU Summary of contents

Page 1

... ATmega16L – 4.5V - 5.5V for ATmega16 • Speed Grades – MHz for ATmega16L – MHz for ATmega16 • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® ® AVR ...

Page 2

... Pin Figure 1. Pinout ATmega16 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega16(L) 2 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 ...

Page 3

... Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. Block Diagram Figure 2 ...

Page 4

... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on 58. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega16( 2466TS–AVR–07/10 ...

Page 7

... UDRE FE DOR TXCIE UDRIE RXEN TXEN ACBG ACO ACI ACIE REFS0 ADLAR MUX4 MUX3 ADSC ADATE ADIF ADIE TWA5 TWA4 TWA3 TWA2 ATmega16(L) Bit 2 Bit 1 Bit – SP10 SP9 SP8 SP2 SP1 SP0 – – IVSEL IVCE – – – – ...

Page 8

... Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. ATmega16(L) 8 Bit 6 ...

Page 9

... Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared 2466TS–AVR–07/10 ATmega16(L) Flags Operation Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 10

... Clear Signed Test Flag SEV Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG ATmega16(L) 10 Flags Operation then PC ← None then PC ← None Rd ← Rr None Rd+1:Rd ← Rr+1:Rr None Rd ← ...

Page 11

... Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2466TS–AVR–07/10 ATmega16(L) Flags Operation H ← None (see specific descr. for Sleep function) None (see specific descr. for WDR/timer) None For On-Chip Debug Only ...

Page 12

... Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 × 7 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega16(L) 12 Ordering Code Package (1) ATmega16L-8AU 44A (1) ATmega16L-8PU 40P6 (1) ATmega16L-8MU 44M1 (1) ATmega16-16AU 44A (1) ATmega16-16PU 40P6 (1) ATmega16-16MU 44M1 Package Type Operation Range Industrial Industrial ...

Page 13

... Orchard Parkway San Jose, CA 95131 R 2466TS–AVR–07/10 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega16(L) A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOTE SYMBOL NOM A – – 1.20 A1 0.05 – ...

Page 14

... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATmega16( PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual ...

Page 15

... Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ATmega16(L) SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 0 ...

Page 16

... ATmega16( ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 17

... Timer/Counter register(TCNTx) is 0x00. 2466TS–AVR–07/10 If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 18

... Update-DR. ATmega16( ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 19

... If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain. If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or ...

Page 20

... Always use OUT or SBI to set EERE in EECR. ATmega16( ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 21

... Mode” on page 140. “Calibrated Internal RC Oscillator” on page “USART Initialization” on page “ATmega16 Boundary-scan Order” on page “ADC Characteristics” on page “I/O Pin Input Hysteresis vs. V “Reset Input Pin Hysteresis vs. V ATmega16(L) Table 120, “Two-wire Serial Bus Require- ...

Page 22

... Characteristics” on page “Ordering Information” on page Table 7 on page 28, Table 15 on page 209, Table 116 on page 276, and “Pinout ATmega16” on page “Analog to Digital Converter” on page “Version” on page 229. “Calibration Byte” on page 261. “Page Size” on page 262. ...

Page 23

... Table 82 on page 217 “Test Access Port – TAP” on page 222 page Figure 126 on page 252. 291. “ATmega16 Typical Characteristics” on page 340. 12. “Programming the Flash” on page 288 289. “Unconnected pins” on page “Filling the Temporary Buffer (Page Loading)” on page 253 ATmega16(L) 36 ...

Page 24

... Added the note at the end of the 6. Corrected description of ADSC bit in on page 7. Improved description on how polarity check of the ADC doff results in Conversion Result” on page ATmega16(L) 24 Table 73, “TWI Bit Rate Prescaler,” on page 182 “TWI Status Register – TWSR” on page “Default Clock Source” on page 31. An extra row and a note added in “ ...

Page 25

... Table 90, “Scan Signals for the Oscillators ATmega16(L) Table 87 on page 229. Table 105 on page 260. are updated to also reflect that AVCC Figure 131 on page 269 added to illustrate “PROG_PAGELOAD ($6)” on page 280 “ATmega16 Typi- “Ordering Information” on (1)(2)(3) ,” on page 235. and 25 ...

Page 26

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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