PIC24FJ256GA106-I/PT Microchip Technology, PIC24FJ256GA106-I/PT Datasheet - Page 15
![IC PIC MCU FLASH 256K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ256GA106-I/PT
Manufacturer Part Number
PIC24FJ256GA106-I/PT
Description
IC PIC MCU FLASH 256K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ256GA106-IPT.pdf
(59 pages)
6.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ256GA106-I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GA106-I/PT
Manufacturer:
AD
Quantity:
201
Company:
Part Number:
PIC24FJ256GA106-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.4
3.4.1
Flash memory write and erase operations are controlled
by the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 3-2) or write operation (Table 3-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation
is complete. Please refer to Section 7.0 “AC/DC
Characteristics and Timing Requirements” for
information about the delays associated with various
programming operations.
TABLE 3-2:
TABLE 3-3:
3.4.2
The WR bit (NVMCON<15>) is used to start an erase or
write cycle. Setting the WR bit initiates the programming
cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
© 2007 Microchip Technology Inc.
404Fh
4042h
4003h
4001h
NVMCON
NVMCON
Value
Value
BSET
Flash Memory Programming in
ICSP Mode
PROGRAMMING OPERATIONS
STARTING AND STOPPING A
PROGRAMMING CYCLE
Write a Configuration Word register.
Program 1 row (64 instruction words) of
code memory or executive memory.
Erase all code memory, executive
memory and Configuration registers
(does not erase Unit ID or Device ID
registers).
Erase a page of code memory or
executive memory.
NVMCON, #WR
NVMCON ERASE
OPERATIONS
NVMCON WRITE
OPERATIONS
Erase Operation
Write Operation
PIC24FJXXXGA1/GB1
3.5
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
404Fh and executing the programming cycle.
A Chip Erase can erase all of user memory or all of both
the user and configuration memory. A table write
instruction should be executed prior to performing the
Chip Erase to select which sections are erased.
When this table write instruction is executed:
• If the TBLPAG register points to user space (is
• If TBLPAG points to configuration space (is
Figure 3-5 shows the ICSP programming process for
performing a Chip Erase. This process includes the
ICSP command code, which must be transmitted (for
each instruction), Least Significant bit first, using the
PGCx and PGDx pins (see Figure 3-2).
FIGURE 3-5:
less than 0x80), the Chip Erase will erase only
user memory.
greater than or equal to 0x80), the Chip Erase will
erase both user and configuration memory.
If configuration memory is erased, the internal
oscillator Calibration Word, located at 0x807FE,
will be erased. This location should be stored prior
to performing a whole Chip Erase and restored
afterward to prevent internal oscillators from
becoming uncalibrated.
Note:
Erasing Program Memory
Program memory must be erased before
writing any data to program memory.
Write 404Fh to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
CHIP ERASE FLOW
Done
Start
DS39907A-page 15