PIC16LF84-04I/SO Microchip Technology, PIC16LF84-04I/SO Datasheet - Page 27
![IC MCU FLASH 1KX14 EE 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF84-04I/SO
Manufacturer Part Number
PIC16LF84-04I/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF84A-04P.pdf
(125 pages)
2.PIC16LF84A-04P.pdf
(4 pages)
3.PIC16LF84-04P.pdf
(108 pages)
Specifications of PIC16LF84-04I/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LC84A-04I/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF84-04I/SO
Manufacturer:
MICROCHIP
Quantity:
3 200
6.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule (Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode TMR0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the T0 source
FIGURE 6-1:
FIGURE 6-2:
RA4/T0CKI
1998 Microchip Technology Inc.
Instruction
Instruction
Executed
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
pin
TMR0
Fetch
PC
TIMER0 MODULE AND TMR0
REGISTER
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
T0SE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
F
TMR0 BLOCK DIAGRAM
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
OSC
PC-1
/4
MOVWF TMR0
T0+1
T0CS
PC
0
1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
Write TMR0
executed
PS2, PS1, PS0
Programmable
PC+1
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
edge select bit, T0SE (OPTION_REG<4>). Clearing bit
T0SE selects the rising edge. Restrictions on the exter-
nal clock input are discussed in detail in Section 6.2.
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled,
(OPTION_REG<3>). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
6.1
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON<2>). The interrupt can be
masked by clearing enable bit T0IE (INTCON<5>). The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
PSout
Read TMR0
reads NT0
NT0
PC+3
(2 cycle delay)
Sync with
TMR0 Interrupt
Internal
clocks
in
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
software,
PSout
TMR0 register
MOVF TMR0,W
Read TMR0
reads NT0 + 1
NT0+1
PIC16F8X
Data bus
PC+5
by
control
8
DS30430C-page 27
Read TMR0
reads NT0 + 2
on Overflow
Set bit T0IF
NT0+2
PC+6
bit
PSA
T0