ATMEGA3250P-20AU Atmel, ATMEGA3250P-20AU Datasheet - Page 133

• Manufacturer Part Number: ATMEGA3250P-20AU
• Description: IC MCU AVR 32K FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250P-20AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3250P-16AU; ATMEGA3250P-16AU

15.11.7
15.11.8
15.11.9
8023F–AVR–07/09
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
TIFR1 – Timer/Counter1 Interrupt Flag Register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “11.” on page
Bit
(0x87)
(0x86)
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
(See Section “11.” on page
See Section “15.3” on page 110.
R/W
(See Section “11.” on page
(See Section “11.” on page
R
7
–
0
7
–
R
0
7
0
R/W
R
6
–
0
6
–
R
0
6
0
53.) is executed when the TOV1 Flag, located in TIFR1, is set.
ICIE1
R/W
ICF1
R/W
R/W
53.) is executed when the ICF1 Flag, located in TIFR1, is set.
5
0
5
0
5
0
R/W
R
4
–
0
R
4
–
0
4
0
53.) is executed when the OCF1B Flag, located in
53.) is executed when the OCF1A Flag, located in
ICR1[15:8]
ICR1[7:0]
R/W
R
3
–
0
R
3
–
0
3
0
ATmega325P/3250P
OCIE1B
OCF1B
R/W
R/W
R/W
2
0
2
0
2
0
OCIE1A
OCF1A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE1
TOV1
R/W
R/W
R/W
0
0
0
0
0
0
TIMSK1
TIFR1
ICR1H
ICR1L
133