PIC18LF2320-I/SP Microchip Technology, PIC18LF2320-I/SP Datasheet - Page 2
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PIC18LF2320-I/SP
Manufacturer Part Number
PIC18LF2320-I/SP
Description
IC MCU FLASH 4KX16 EEPROM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2220-ISO.pdf
(394 pages)
3.PIC18F2220-ISO.pdf
(6 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(8 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18LF2320-I/SP
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2220/2320/4220/4320
3. Module: Internal Oscillator Block
4. Module: INTOSC
DS80156G-page 2
At high temperature (above 85°C) or low V
(below 2.5V), the IOFS bit (OSCCON<2>) may not
become set when the internal oscillator block is
selected as the system clock source for any
frequency above 31 kHz (OSCCON<6:4>
The INTOSC output will stabilize at 8 MHz;
however, the IOFS bit may not become set.
Work around
If time critical code is to be executed, it should be
delayed by 1 ms following the operation that
enables the 8 MHz INTOSC output from the
internal oscillator block.
Date Codes that pertain to this issue:
All engineering and production devices.
Incrementing or decrementing the value in the
OSCTUNE register may not have the expected
effect of shifting the INTRC or INTOSC output
frequencies. The OSCTUNE values beyond which
this happens may vary with temperatures above
70°C.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
≠
000).
DD
5. Module: MSSP (All I
The Buffer Full flag bit (BF) of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared,
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR
• Any instruction that contains C9h in its 8 Least
Work around
Identified work arounds will involve setting the
contents of BSR<3:0> to some value other than
0Fh.
In addition to those proposed below, other solutions
may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
Date Codes that pertain to this issue:
All engineering and production devices.
register are equal to 0Fh (BSR<3:0> = 1111)
and
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
these guidelines in mind:
• Assign 12-bit addresses to all variables.
• Do not set the BSR to point to Bank 15
• Allow the assembler to manipulate the
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least Signifi-
cant bits while the BSR points to Bank 15
(BSR = 0Fh).
This allows the assembler to know when
Access Banking can be used.
(BSR = 0Fh).
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
© 2007 Microchip Technology Inc.
2
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