PIC18F4525-I/ML Microchip Technology, PIC18F4525-I/ML Datasheet - Page 6
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PIC18F4525-I/ML
Manufacturer Part Number
PIC18F4525-I/ML
Description
IC MCU FLASH 24KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
Specifications of PIC18F4525-I/ML
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3968Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Package
44QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3DB18F4620 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
PIC18F2525/2620/4525/4620
20. Module: Interrupts
EXAMPLE 2:
DS80224E-page 6
ISR @ 0x0008
Foo:
CALL
POP
:
:
RETFIE
If an interrupt occurs during a two-cycle instruction
that modifies the STATUS, BSR or WREG register,
the unmodified value of the register will be saved
to the corresponding Fast Return (Shadow)
register and upon a fast return from the interrupt,
the unmodified value will be restored to the
STATUS, BSR or WREG register.
For example, if a high priority interrupt occurs
during the instruction, MOVFF TEMP, WREG, the
MOVFF instruction will be completed and WREG
will be loaded with the value of TEMP before
branching to ISR. However, the previous value of
WREG will be saved to the Fast Return register
during ISR branching. Upon return from the
interrupt with a fast return, the previous value of
WREG in the Fast Return register will be written to
WREG. This results in WREG containing the value
it had before execution of MOVFF TEMP, WREG.
Affected instructions are:
MOVFF Fs, Fd
where Fd is WREG, BSR or STATUS;
MOVSF Zs, Fd
where Fd is WREG, BSR or STATUS; and
MOVSS [Zs], [Zd]
where the destination is WREG, BSR or STATUS.
Foo, FAST
FAST
; store current value of WREG, BSR, STATUS for a second time
; clears return address of Foo call
; insert high priority ISR code here
Work around
1. Assembly Language Programming:
a) If any two-cycle instruction is used to modify
b) As another alternative, the following work
Date Codes that pertain to this issue:
the WREG, BSR or STATUS register, do not
use the RETFIE FAST instruction to return
from the interrupt. Instead, save/restore
WREG, BSR and STATUS via software per
Example 8-1 in the Device Data Sheet. Alter-
natively, in the case of MOVFF, use the MOVF
instruction to write to WREG instead. For
example, use:
MOVF
MOVWF
instead of MOVFF TEMP, BSR.
around shown in Example 2 can be used.
This example overwrites the Fast Return
register by making a dummy call to Foo with
the fast option in the high priority service
routine.
All engineering and production devices.
TEMP, W
BSR
© 2008 Microchip Technology Inc.