PIC24HJ128GP310-I/PT Microchip Technology, PIC24HJ128GP310-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC24HJ128GP310-I/PT
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ128GP310-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• No. Of Pwm Channels: 8
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

38. DMA
39. DMA
40. DMA
41. REPEAT Instruction
42. FRC Oscillator
43. UART Module
44. SPI Module
45. I
46. I
© 2008 Microchip Technology Inc.
NULL Data Peripheral Write mode for the DMA
channel does not function.
DMA request Fault condition does not generate a
DMA error trap.
DMA channel writes an additional NULL value to
the peripheral register.
Any instruction executed inside a REPEAT loop
that produces a Read-After-Write stall condition,
results in the instruction being executed fewer
times than was intended.
For certain values of the TUN<5:0> bits
(OSCTUN<5:0>), the resultant frequencies are
incorrect.
The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
The SPIxCON1 DISSCK bit does not influence
port functionality.
The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
2
2
C Module
C Module: 10-bit addressing mode
2
C module is configured for 10-bit
2
C devices, the A10 and A9 bits may
PIC24HJXXXGPX06/X08/X10
47. I
48. I
49. I
50. Internal Voltage Regulator
51. ECAN Module
52. PSV Operations
53. UART (UxE Interrupt)
54. UART Module
The following sections describe the errata and work
around to these errata, where they may apply.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
With the I
external
associated with SCL and SDA pins will not reflect
the actual digital logic levels on the pins.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the VREGS (RCON<8>) bit is set to a logic
‘0’, higher sleep current may be observed.
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
When the UART module is operating in 8-bit mode
(PDSEL
encoder/decoder
incorrectly transmits a data payload of 80h as 00h.
2
2
2
C Module: 10-bit Addressing Mode
C Module
C Module: 10-bit Addressing Mode
2
Interrupt
C module enabled, the PORT bits and
=
2
C module is configured as a 10-bit
0x)
(IREN
Input
and
=
using
functions
1),
DS80280G-page 3
the
the
(if
module
IrDA
any)
®