PIC16LF876-04I/SP Microchip Technology, PIC16LF876-04I/SP Datasheet - Page 72
PIC16LF876-04I/SP
Manufacturer Part Number
PIC16LF876-04I/SP
Description
IC MCU FLASH 8KX14 EE A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF876-04I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP, PSP, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF876-04I/SP
Manufacturer:
MICROCHIP
Quantity:
4 000
Part Number:
PIC16LF876-04I/SP
Manufacturer:
MICRCOHI
Quantity:
20 000
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PIC16F87X
9.1.1
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 9-2:
DS30292C-page 70
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
MASTER MODE
SPI MODE TIMING, MASTER MODE
bit7
bit7
bit7
bit6
bit5
bit4
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit3
CY
)
bit2
CY
CY
)
)
2001 Microchip Technology Inc.
bit1
bit0
bit0
bit0
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