PIC16C74B-04I/P Microchip Technology, PIC16C74B-04I/P Datasheet - Page 94
![IC MCU OTP 4KX14 A/D PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16C74B-04I/P
Manufacturer Part Number
PIC16C74B-04I/P
Description
IC MCU OTP 4KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
5.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C74B-04I/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
192Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C74B-04I/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16C74B-04I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16C63A/65B/73B/74B
FIGURE 13-5:
13.5.1
The external interrupt on RB0/INT pin is edge trig-
gered: either rising if bit INTEDG (OPTION_REG<6>)
is set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 13.8 for details on SLEEP mode.
13.5.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (see Section 6.0).
DS30605C-page 94
The following table shows which devices have which interrupts.
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
PSPIF
PSPIE
CCP2IF
CCP2IE
Device
ADIF
ADIE
INT INTERRUPT
TMR0 INTERRUPT
TMR1IF
TMR1IE
T0IF
Yes
Yes
Yes
Yes
RCIF
RCIE
TMR2IF
TMR2IE
00h) in the TMR0 register will set
INTERRUPT LOGIC
INTF
Yes
Yes
Yes
Yes
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
RBIF
Yes
Yes
Yes
Yes
PSPIF
Yes
Yes
–
–
ADIF
Yes
Yes
–
–
RCIF
Yes
Yes
Yes
Yes
TXIF
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Yes
Yes
Yes
Yes
13.5.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note:
SSPIF
Yes
Yes
Yes
Yes
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
PORTB INTERRUPT-ON-CHANGE
CCP1IF
Yes
Yes
Yes
Yes
TMR2IF
Yes
Yes
Yes
Yes
2000 Microchip Technology Inc.
Wake-up (If in SLEEP mode)
TMR1IF
Yes
Yes
Yes
Yes
Interrupt to CPU
CCP2IF
Yes
Yes
Yes
Yes