PIC18F452-I/P Microchip Technology, PIC18F452-I/P Datasheet - Page 243

• Manufacturer Part Number: PIC18F452-I/P
• Description: IC MCU FLASH 16KX16 EE 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC18F452I/P; Q1176145

RCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
2002 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
No
PC =
PC =
TOS =
Q1
Read literal
Push PC to
Address (HERE)
Address (Jump)
Address (HERE+2)
operation
Relative Call
[ label ] RCALL
-1024
(PC) + 2
(PC) + 2 + 2n
None
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
1
2
HERE
stack
1101
No
Q2
’n’
n
RCALL
1nnn
TOS,
operation
1023
Process
Data
No
Q3
PC
Jump
n
nnnn
Write to PC
operation
No
Q4
nnnn
RESET
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
After Instruction
Decode
Registers =
Flags*
Q1
=
Reset
[ label ]
None
Reset all registers and flags that
are affected by a MCLR Reset.
All
This instruction provides a way to
execute a MCLR Reset in software.
1
1
RESET
reset
Start
0000
Q2
Reset Value
Reset Value
PIC18FXX2
RESET
0000
operation
No
Q3
DS39564B-page 241
1111
operation
No
Q4
1111