AT89C51CC03U-RDRIM Atmel, AT89C51CC03U-RDRIM Datasheet - Page 148

• Manufacturer Part Number: AT89C51CC03U-RDRIM
• Description: IC 8051 MCU FLASH 64K 64VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC03U-RDRIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT89C51CC03URDRTR

ADC Converter
Operation
Voltage Conversion
Clock Selection
Figure 71. A/D Converter clock
ADC Standby Mode
148
AT89C51CC03
CPU Core Clock Symbol
CLOCK
CPU
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (see Figure 72). Clear this flag for re-
arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Table 101. Selected Analog input
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range! (See section
“AC-DC”)
The ADC clock is the same as CPU.
The typical maximum clock frequency for ADC is 700 KHz. A prescaler is featured
(ADCCLK) to generate the ADC clock from the oscillator frequency.
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register. In this mode its power dissipation is about 1 µW.
SCH2
÷
0
0
0
0
1
1
1
1
2
Prescaler ADCLK
SCH1
0
0
1
1
0
0
1
1
ADC Clock
SCH0
0
1
0
1
0
1
0
1
Converter
Selected Analog input
4182E–CAN–05/04
A/D
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7