PIC18F452-I/ML Microchip Technology, PIC18F452-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC18F452-I/ML
• Description: IC MCU FLASH 16KX16 A/D 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 3-3:
FIGURE 3-3:
 2010 Microchip Technology Inc.
Step 1: Direct access to config memory.
Step 2: Configure device for multi-panel writes.
Step 3: Direct access to code memory and enable erase.
Step 4: Erase single row of all panels at an offset.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1111
0000
4-Bit
8E A6
8C A6
86 A6
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
8E A6
9C A6
88 A6
6A F8
6A F7
6A F6
<DummyLSB>
<DummyMSB>
00 00
ERASE CODE MEMORY CODE SEQUENCE
Data Payload
MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
Addr = Addr + 64
BSF
BSF
BSF
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
BSF
BCF
BSF
CLRF
CLRF
CLRF
Write 2 dummy bytes and start programming.
NOP - hold SCLK high for time P9.
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, EEPGD
EECON1, CFGS
EECON1, FREE
TBLPTRU
TBLPTRH
TBLPTRL
No
Start Erase Sequence
and Hold SCLK High
Multi-Panel Erase
Delay P9 + P10
Time for Erase
Until Done
Device for
Configure
to Occur
panels
done?
Start
Done
Core Instruction
All
Yes
Addr = 0
PIC18FXX2/XX8
DS39576C-page 9