PIC16LF874-04I/L Microchip Technology, PIC16LF874-04I/L Datasheet - Page 105

• Manufacturer Part Number: PIC16LF874-04I/L
• Description: IC MCU FLASH 4KX14 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF874-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF874-04I/LR; PIC16LF874-04I/LR

10.2.3
When setting up an Asynchronous Reception with
Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
• Enable the asynchronous serial port by clearing
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 10-6:
baud rate. If a high speed baud rate is desired, set
bit BRGH.
bit SYNC and setting bit SPEN.
2001 Microchip Technology Inc.
F
OSC
RC7/RX/DT
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
Baud Rate Generator
x64 Baud Rate CLK
USART RECEIVE BLOCK DIAGRAM
SPBRG
Pin Buffer
and Control
RSR<8>
SPEN
ADDEN
ADDEN
RX9
RX9
Data
Recovery
Interrupt
or
64
16
CREN
Enable
Load of
Receive
Buffer
RCIF
RCIE
• Flag bit RCIF will be set when reception is com-
• Read the RCSTA register to get the ninth bit and
• Read the 8-bit received data by reading the
• If any error occurred, clear the error by clearing
• If the device has been addressed, clear the
RX9
plete, and an interrupt will be generated if enable
bit RCIE was set.
determine if any error occurred during reception.
RCREG register, to determine if the device is
being addressed.
enable bit CREN.
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
STOP
MSb
RX9D
(8)
OERR
7
RSR Register
RCREG Register
8
Data Bus
8
8
PIC16F87X
1
FERR
0
START
LSb
FIFO
DS30292C-page 103