PIC16C74A-20/P Microchip Technology, PIC16C74A-20/P Datasheet - Page 40
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PIC16C74A-20/P
Manufacturer Part Number
PIC16C74A-20/P
Description
IC MCU OTP 4KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C72-04SO.pdf
(289 pages)
5.PIC16LC74A-04P.pdf
(8 pages)
Specifications of PIC16C74A-20/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Package
40PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
33
Interface Type
I2C/SPI/USART
On-chip Adc
8-chx8-bit
Number Of Timers
3
Core
PIC
Processor Series
PIC16C
Maximum Clock Frequency
20 MHz
Data Ram Size
192 B
Data Rom Size
192 B
Mounting Style
Through Hole
A/d Bit Size
8 bit
A/d Channels Available
8
Height
3.81 mm
Length
52.26 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Supply Voltage (max)
6 V
Supply Voltage (min)
4 V
Width
13.84 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C74A-20/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16C74A-20/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16C7X
4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 4-17 shows the two situa-
tions for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3>
FIGURE 4-17: LOADING OF PC IN
4.3.1
A computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30390E-page 40
PC
PC
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
STACK
Applicable Devices
72 73 73A 74 74A 76 77
PCH
5
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
DIFFERENT SITUATIONS
7
7
PCH). The lower example in
PCL
PCL
11
8
0
0
PCH).
Instruction with
PCL as
Destination
ALU
GOTO, CALL
Opcode <10:0>
4.4
PIC16C7X devices are capable of addressing a contin-
uous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper 2 bits
of the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is pushed onto the stack. Therefore,
manipulation of the PCLATH<4:3> bits are not required
for the return instructions (which POPs the address
from the stack).
Note:
Note 1: There are no status bits to indicate stack
Note 2: There are no instructions/mnemonics
Program Memory Paging
Applicable Devices
72 73 73A 74 74A 76 77
PIC16C7X devices with 4K or less of pro-
gram
PCLATH<4>. The use of PCLATH<4> as a
general purpose read/write bit is not rec-
ommended since this may affect upward
compatibility with future products.
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
memory
1997 Microchip Technology Inc.
ignore
paging
bit