DSPIC33FJ256MC710-I/PF Microchip Technology, DSPIC33FJ256MC710-I/PF Datasheet - Page 328

• Manufacturer Part Number: DSPIC33FJ256MC710-I/PF
• Description: IC DSPIC MCU/DSP 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC710-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 30K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 30 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJXXXMCX06/X08/X10
TABLE A-1:
DS70287C-page 326
Section 8.0 “Oscillator Configuration”
Section 15.0 “Motor Control PWM Module” Removed sections 15.1 through 15.16 (redundant information,
Section 16.0 “Quadrature Encoder
Interface (QEI) Module”
Section 17.0 “Serial Peripheral Interface
(SPI)”
Section 18.0 “Inter-Integrated Circuit™
(I
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 20.0 “Enhanced CAN (ECAN™)
Module”
Section 21.0 “10-Bit/12-Bit Analog-to-
Digital Converter (ADC)”
2
C™)”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Updated the third clock source item (External Clock) in
Section 8.1.1 “System Clock Sources”.
Added the center frequency in the OSCTUN register for the FRC
Tuning bits (TUN<5:0>) value 011111 and updated the center
frequency for bits value 011110 (Register 8-4).
which is now available in the related section in the “dsPIC33F
Family Reference Manual”).
Updated SFR names in the PWM Module Block Diagram (Figure 15-
1).
Updated all register names (Register 16-1 through Register 15-15).
Removed sections 16.1 through 16.9 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated names in Quadrature Encoder Interface Block Diagram
(Figure 16-1).
Updated register names (Register 16-1 and Register 16-2).
Removed redundant information, which is now available in the
related section in the “dsPIC33F Family Reference Manual”.
Removed sections 18.3 through 18.14, while retaining the I
Diagram (Figure 18-1) (redundant information, which is now
available in the related section in the “dsPIC33F Family Reference
Manual”).
Removed sections 19.1 through 19.7 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Removed sections 20.4 through 20.6 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1
register (Register 20-9).
Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15
(FLTEN6-FLTEN15) in the CiFEN1 register (Register 20-11).
Removed Equation 21-1 (ADC Conversion Clock Period) and Figure
21-3 (ADC Transfer Function (10-Bit Example) in Section 21.0 “10-
bit/12-bit Analog-to-Digital Converter (ADC)”
Updated AN14 and AN15 ADC values in the ADC2 Module Block
Diagram (Figure 21-2).
Added Note 2 to ADC Conversion Clock Period Block Diagram
(Figure 21-3).
Added Note to ADxCHS0 register (Register 21-6).
Updated ADC Conversion Clock Select bits in the ADxCON3
register from ADCS<5:0> to ADCS<7:0>. Any references to these
bits have also been updated throughout this data sheet
(Register 21-3).
Update Description
© 2009 Microchip Technology Inc.
2
C Block