PIC32MX675F256L-80I/PF Microchip Technology, PIC32MX675F256L-80I/PF Datasheet - Page 100
![IC MCU 32BIT 256KB FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC32MX675F256L-80I/PF
Manufacturer Part Number
PIC32MX675F256L-80I/PF
Description
IC MCU 32BIT 256KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F256L-80I/PF
Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX6xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F256L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- PIC32MX575F256H-80IPT PDF datasheet #5
- Current page: 100 of 254
- Download datasheet (6Mb)
TABLE 4-40:
Legend:
Note
40A0
40C0 CHEPFABT
4000 CHECON
4010 CHEACC
4020 CHETAG
4030 CHEMSK
4040
4050
4060
4070
4080
4090
1:
2:
CHELRU
CHEMIS
CHEW0
CHEW1
CHEW2
CHEW3
CHEHIT
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
Reset value is dependent on DEVCFGx configuration.
(1,2)
(1)
(1)
(1)
31:16
31:16 CHEWEN
31:16 LTAGBOOT
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PREFETCH REGISTER MAP
31/15
—
—
—
—
—
30/14
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
LMASK<15:5>
26/10
—
—
—
—
—
—
—
LTAG<15:4>
25/9
—
—
—
—
—
—
DCSZ<1:0>
CHEPFABT<31:0>
24/8
CHELRU<15:0>
CHEMIS<31:0>
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
CHEHIT<31:0>
—
—
—
—
—
Bits
23/7
—
—
—
—
—
22/6
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
21/5
PREFEN<1:0>
—
—
—
—
CHELRU<24:16>
20/4
—
—
—
—
—
LTAG<23:16>
LVALID
19/3
—
—
—
—
—
LLOCK
18/2
—
—
CHEIDX<3:0>
—
—
PFMWS<2:0>
for more information.
LTYPE
17/1
—
—
—
—
CHECOH 0000
16/0
—
—
—
—
0007
0000
0000
00xx
xx20
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
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