DSPIC30F6013A-30I/PT Microchip Technology, DSPIC30F6013A-30I/PT Datasheet - Page 60
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DSPIC30F6013A-30I/PT
Manufacturer Part Number
DSPIC30F6013A-30I/PT
Description
IC DSPIC MCU/DSP 132K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6011A-30IPT.pdf
(234 pages)
3.DSPIC30F6011A-30IPT.pdf
(8 pages)
4.DSPIC30F6011A-30IPT.pdf
(10 pages)
5.DSPIC30F6011A-30IPT.pdf
(6 pages)
6.DSPIC30F6011A-30IPT.pdf
(8 pages)
7.DSPIC30F6011A-30IPT.pdf
(16 pages)
8.DSPIC30F6014A-20EPT.pdf
(238 pages)
9.DSPIC30F6011A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6013A-30I/PT
Program Memory Type
FLASH
Program Memory Size
132KB (44K x 24)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
68
Data Ram Size
6 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300024, DM330011
Minimum Operating Temperature
- 40 C
Core Frequency
30MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Operating Temperature Range
-40°C To
Rohs Compliant
Yes
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F6013A30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013A-30I/PT
Manufacturer:
Microchip
Quantity:
1 096
Company:
Part Number:
DSPIC30F6013A-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
APPENDIX A:
A.1
The checksum computation is described in
“Checksum
16-bit computation can be made for each dsPIC30F
device. Computations for read code protection are
shown both enabled and disabled. The checksum
values assume that the Configuration registers are also
erased. However, when code protection is enabled, the
value of the FGS register is assumed to be 0x5.
TABLE A-1:
DS70102K-page 60
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013
dsPIC30F5015
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB
Device
Checksum Computation
Computation”.
= Configuration Block (masked) = Byte sum of ((FOSC&0xC10F) + (FWDT&0x803F) +
(FBORPOR&0x87B3) + (FBS&0x310F) + (FSS&0x330F) + (FGS&0x0007) + (FICD&0xC003))
CHECKSUM COMPUTATION
DEVICE-SPECIFIC
INFORMATION
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Read Code
Protection
Table A-1
shows how this
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
Section 6.8
Checksum Computation
A.2
A.2.1
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
with 0x0000 before the device is chip erased. The steps
to perform this action are shown in
A.2.2
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
with 0x0000 using the PROGC command before the
ERASEB command is used to erase the chip.
dsPIC30F5011 and dsPIC30F5013
ICSP PROGRAMMING
ENHANCED ICSP PROGRAMMING
0xD406
0xD406
0xD406
0xA406
0xA406
0xA406
0xA406
0xA406
0xFC06
0xFC06
0xFC06
Erased
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x4406
0x0404
0x4406
0x0404
0x4406
0x0404
0x0404
0x0404
0x0404
Value
© 2010 Microchip Technology Inc.
0xAAAAAA at 0x0
Code Address
Table
Value with
and Last
0xD208
0xD208
0xD208
0x0404
0x0404
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0x4208
0x0404
0x4208
0x0404
0x4208
0x0404
0xFA08
0x0404
0xFA08
0x0404
0xFA08
0x0404
11-4.