PIC17C756A-33I/L Microchip Technology, PIC17C756A-33I/L Datasheet - Page 139
PIC17C756A-33I/L
Manufacturer Part Number
PIC17C756A-33I/L
Description
IC MCU OTP 16KX16 A/D PWM 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
50
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Controller Family/series
PIC17
No. Of I/o's
50
Ram Memory Size
902Byte
Cpu Speed
33MHz
No. Of Timers
4
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
4
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
68PLCC
Device Core
PIC
Family Name
PIC17
Maximum Speed
33 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC17C756A-33I/L
Manufacturer:
Microchip Technology
Quantity:
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15.1.4
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-5) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON1<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 15-6:
2000 Microchip Technology Inc.
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit7
bit7
bit7
bit7
bit6
bit6
bit5
bit5
bit4
bit4
Figure 15-6, Figure 15-8 and Figure 15-9, where the
MSb is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 33 MHz)
of 8.25 MHz.
Figure 15-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
bit3
bit3
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit2
bit2
CY
)
bit1
bit1
CY
CY
)
)
PIC17C7XX
bit0
bit0
bit0
bit0
DS30289B-page 139
Next Q4 cycle
after Q2
4 clock
modes
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