AT91SAM9261B-CU Atmel, AT91SAM9261B-CU Datasheet
AT91SAM9261B-CU
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AT91SAM9261B-CU Summary of contents
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... Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals ® ® Thumb Processor ® Acceleration ™ ® AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6062LS–ATARM–23-Mar-09 ...
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... Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel EEPROMs Supported ® • IEEE 1149.1 JTAG Boundary Scan on All Digital Pins • ...
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Description The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for ...
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Block Diagram Figure 2-1. AT91SAM9261 Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG ...
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Signal Description Table 3-1. Signal Description by Peripheral Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDPLL PLL Power Supply VDDOSC Oscillator Power Supply VDDCORE Core ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Controller Chip Select BA0 - BA1 Bank Select SDWE SDRAM Write Enable RAS - CAS Row and Column Signal SDA10 SDRAM ...
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock LCDD0 - LCDD23 LCD Data Bus LCDVSYNC LCD Vertical Synchronization LCDHSYNC LCD Horizontal Synchronization LCDDOTCK LCD Dot Clock LCDDEN LCD Data Enable ...
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Package and Pinout The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9261 Mechanical ...
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Pinout Table 4-1. AT91SAM9261 Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC ...
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Power Considerations 5.1 Power Supplies The AT91SAM9261 has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: ...
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Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma- nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this ...
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Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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Debug and Test Features • Integrated Embedded In-circuit Emulator Real-Time – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • ...
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Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • Nineteen channels – Two for each USART – Two for the ...
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Memories Figure 8-1. AT91SAM9261 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space ...
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Internal Memory Mapping Table 8-3 status and the BMS state at reset. Table 8-3. Internal Memory Mapping Address Master 0: ARM926 Instruction REMAP(RCB0 BMS = 1 0x0000 0000 Int. ROM Note: 1. EBI NCS0 ...
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The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software ...
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Boot Strategies The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank ...
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ETM Memories The eight ETM9 Medium+ memory map decoder inputs are connected to custom address decoders and the resulting memory mapping is summarized in Table 8-6. Product Resource SRAM SRAM ROM ROM External Bus Interface External Bus Interface ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF ...
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Block Diagram Figure 9-1. System Controller Block Diagram periph_irq[2..21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset VDDCORE Powered NRST VDDCORE POR VDDBU POR backup_nreset SHDN WKUP backup_nreset VDDBU Powered XIN32 SLOW CLOCK XOUT32 OSC XIN MAIN OSC ...
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Reset Controller • Based on two Power-on-Reset cells • Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset • Controls the internal resets and the NRST pin output 9.3 ...
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Power Management Controller • The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – thirty peripheral clocks – ...
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... Chip ID Registers – ICE Access Prevention • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
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Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of • ICE Access prevention – Enables software to prevent system access ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory ...
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Peripheral Multiplexing on PIO Lines The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one ...
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Timer Counter channels’ outputs and trigger inputs • using the SSC2 10.3.1.5 NAND Flash Interface Using the NAND Flash interface prevents: • using NCS3, NCS6 and NCS7 to access other parallel devices 10.3.1.6 Compact Flash Interface ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO MCDA0 PA1 SPI0_MOSI MCCDA PA2 SPI0_SPCK MCCK PA3 SPI0_NPCS0 PA4 SPI0_NPCS1 MCDA1 PA5 SPI0_NPCS2 MCDA2 PA6 SPI0_NPCS3 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 LCDVSYNC PB1 LCDHSYNC PB2 LCDDOTCK PCK0 (1) PB3 LCDDEN PB4 LCDCC LCDD2 PB5 LCDD0 LCDD3 PB6 LCDD1 LCDD4 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Peripheral B PC0 NANDOE NCS6 PC1 NANDWE NCS7 PC2 NWAIT IRQ0 PC3 A25/CFRNW PC4 NCS4/CFCS0 PC5 NCS5/CFCS1 PC6 CFCE1 PC7 CFCE2 ...
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System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • ...
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Static Memory Controller • External memory mapping, 256 Mbyte address space per Chip Select Line • Eight Chip Select Lines • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte ...
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Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, ...
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Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I more). • Contains an independent receiver ...
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USB • USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with ...
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Package Drawing Figure 11-1. 217-ball LFBGA Package Drawing 6062LS–ATARM–23-Mar-09 AT91SAM9261 Preliminary 39 ...
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... Ordering Information Table 12-1. AT91SAM9261 Ordering Information Ordering Code MRL AT91SAM9261-CJ AT91SAM9261B-CU AT91SAM9261 Preliminary 40 Package Package Type A BGA217 RoHS-compliant B BGA217 Temperature Operating Range Industrial -40°C to 85°C Industrial Green -40°C to 85°C 6062LS–ATARM–23-Mar-09 ...
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Revision History Table 13-1. Revision History Doc. Rev. Source Comments 6062AS Qualified/Internal: 23-Aug-04 Date: 02-Jun-05 Change to Additional Embedded Memories in CSR 04-370 Consumption” on page Change to AIC, CSR 04-371 Peripheral,” on page Added NTRST signal CSR 04-376 ...
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Table 13-1. Revision History (Continued) Doc. Rev. Source Comments Corrected MIPS and speed on page 1. 6062DS 2292 Added information on EBI NCS0 hwhen BMS = 0 in Updated information on JTAGSEL in 2946 Section 6.1 “JTAG Port Pins” on ...
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Table 13-1. Revision History (Continued) Doc. Rev. Source Comments 5846 In Features, on page 2 6062KS Debug Unit (DBGU) updated 5932 Section 10.9 5424/rfo Section 8.1.2.1 “BMS = 1, Boot on Embedded 6062LS Section 12. “Ordering updated with ordering information ...
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