Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 133

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

PS022008-0810
PWM Duty Cycle Registers
Independent and Complementary PWM Outputs
Center-Aligned PWM Mode Period
EDGE-ALIGNED Mode
In EDGE-ALINGED PWM mode, a 12-bit up counter creates the PWM period with a
minimum resolution equal to the PWM clock source period. The counter counts up to the
Reload value, resets to
CENTER-ALINGED Mode
In CENTER-ALINGED PWM mode, a 12-bit up/down counter creates the PWM period
with a minimum resolution equal to twice the PWM clock source period. The counter
counts up to the Reload value and then counts down to 0.
The PWM duty cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D,
PWMH2D, PWML2D) contain a 16-bit signed value where bit 15 is the sign bit. The duty
cycle value is compared to the current 12-bit unsigned PWM count value. If the PWM
duty cycle value is set less than or equal to 0, the PWM output is deasserted for full PWM
period. If the PWM duty cycle value is set to a value greater than the PWM Reload value,
the PWM output is asserted for full PWM period.
The six PWM outputs are configured to operate independently or as three complementary
pairs. Operation as six independent PWM channels are enabled by setting the INDEN bit
in the
output uses its own PWM duty cycle value.
When PWM outputs are configured to operate as three complementary pairs, the PWM
duty cycle values PWMH0D, PWMH1D, and PWMH2D control the modulator output. In
COMPLEMENTARY OUTPUT mode deadband time is also inserted.
The POLx bits in the
the high- and low-side signals. As illustrated in
when the POLx bits are cleared to 0, the PWM high-side output will start in the on-state
Edge-Aligned PWM Mode Period
PWM Control 1 Register
PWM Control 1 Register (PWMCTL1)
000H
P R E L I M I N A R Y
, and then resumes counting.
(PWMCTL1). In INDEPENDENT mode, each PWM
=
=
2 Prescaler
--------------------------------------------------------------------- -
Prescaler Reload Value
------------------------------------------------------------ -

Figure 21
f
PWMclk

f
PWMclk

and
Reload Value
select the relative polarity of
Figure 22
Multi-Channel PWM Timer
Product Specification
ZNEO
on page 117,
Z16F Series
118