EZ80F91AZ050EG Zilog, EZ80F91AZ050EG Datasheet - Page 99
EZ80F91AZ050EG
Manufacturer Part Number
EZ80F91AZ050EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91AZ050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3867
EZ80F91AZ050EG
EZ80F91AZ050EG
Available stocks
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Manufacturer
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PS019215-0910
Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles
Normal bus operation of the eZ80F91 device using CS0 to communicate to an external
peripheral is displayed in
bus master communicating with an external peripheral during bus acknowledge cycles.
Pin Symbol
ADDR23..ADDR0
CS0
CS1
CS2
CS3
DATA7..0
IORQ
MREQ
RD
WR
INSTRD
Signal Direction
Input
Output
Output
Output
Output
Tristate
Input
Input
Tristate
Tristate
Tristate
Figure 20
on page 91.
Description
Allows external bus master to utilize the chip
select logic of the eZ80F91.
Normal operation.
Normal operation.
Normal operation.
Normal operation.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to utilize the chip
select logic of the eZ80F91.
Allows external bus master to utilize the chip
select logic of the eZ80F91.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to communicate
with external peripherals.
Figure 21
on page 91 displays an external
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
90
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