C8051F997-GU Silicon Laboratories Inc, C8051F997-GU Datasheet - Page 55

• Manufacturer Part Number: C8051F997-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F997-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Cap Sense, POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, Enhanced UART, Enhanced SPI
• Maximum Clock Frequency: 7 KHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F996DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 1 Analog Comparator
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1946-5

Table 4.4. Reset Electrical Characteristics
V
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
VDD Monitor Threshold
(V
VDD Ramp Time for Power
On
POR Monitor Threshold
(V
Missing Clock Detector
Timeout
Minimum System Clock w/
Missing Clock Detector
Enabled
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V
V
Current
DD
DD
DD
RST
POR
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Monitor Turn-on Time
Monitor Supply 
)
)
Parameter
Time from last system clock rising edge
Recovery from Brownout (VDD Rising)
System clock frequency which triggers
Delay between release of any reset
Brownout Condition (VDD Falling)
a missing clock detector timeout
(all power modes except Sleep)
execution at location 0x0000
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
VBAT Ramp from 0–1.8 V
V
V
V
V
source and code
to reset initiation
DD
DD
DD
DD
Early Warning
Reset Trigger
I
OL
Conditions
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 1.4 mA,
Rev. 1.0
C8051F99x-C8051F98x
V
0.7 x V
DD
0.45
Min
100
1.8
1.7
15
—
—
—
—
—
—
—
—
—
—
—
– 0.6
DD
1.85
1.75
1.75
Typ
650
300
0.7
—
—
—
—
—
20
—
10
—
4
7
7
0.3 x V
1000
Max
0.6
0.6
1.9
1.8
1.0
30
10
—
—
—
—
—
—
—
—
3
DD
Units
kHz
µA
ms
µA
µs
µs
µs
ns
V
V
V
V
V
V
V
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