MC9S08GT8AMFDE Freescale Semiconductor, MC9S08GT8AMFDE Datasheet - Page 138
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MC9S08GT8AMFDE
Manufacturer Part Number
MC9S08GT8AMFDE
Description
IC MCU 8K FLASH 1K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT8ACFBER.pdf
(300 pages)
Specifications of MC9S08GT8AMFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
39
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48QFN EP
Family Name
HCS08
Maximum Speed
40 MHz
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Internal Clock Generator (S08ICGV4)
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
9.4.3
FLL engaged internal (FEI) is entered when any of the following conditions occur:
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
138
•
•
CLKS bits are written to 01
The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
FLL Engaged, Internal Clock (FEI) Mode
DCOS
COUNTER ENABLE
CLKST
SUBTRACTOR
REFERENCE
DIVIDER (/7)
RANGE
Figure 9-13. Detailed Frequency-Locked Loop Block Diagram
LOCK
MFD
RANGE
OVERFLOW
LOSS OF CLOCK
LOLS
DETECTOR
LOCK AND
MC9S08GT16A/GT8A Data Sheet, Rev. 1
LOCS
ICGIRCLK
ERCS
DIGITAL
CLKST
FILTER
LOOP
FLT
LOCD
COUNTER
PULSE
ICGIF
CONTROLLED
OSCILLATOR
FLL ANALOG
DIGITALLY
INTERRUPT
RESET AND
CIRCUIT
SELECT
CLOCK
CONTROL
CLKS
LOLRE
ICGDCLK
ICG2DCLK
1x
2x
LOCRE
FREQUENCY
DIVIDER (R)
REDUCED
RFD
Freescale Semiconductor
FREQUENCY-
LOOP (FLL)
LOCKED
ICGOUT
RESET
IRQ
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