MC9S08AC16CBE Freescale Semiconductor, MC9S08AC16CBE Datasheet - Page 222
![IC MCU 8BIT 16K FLASH 42SDIP](/photos/39/70/397054/pdip42_sml.jpg)
MC9S08AC16CBE
Manufacturer Part Number
MC9S08AC16CBE
Description
IC MCU 8BIT 16K FLASH 42SDIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08AC16CBE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
Package
42SPDIP
Family Name
HCS08
Maximum Speed
40 MHz
On-chip Adc
8-chx10-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Serial Peripheral Interface (S08SPIV3)
in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input
of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.
222
(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
MSB FIRST
BIT TIME #
(CPOL = 0)
(CPOL = 1)
LSB FIRST
(MASTER)
(SLAVE)
SS OUT
SPSCK
SPSCK
SS IN
MOSI
MISO
BIT 7
BIT 0
1
Figure 12-11. SPI Clock Formats (CPHA = 0)
MC9S08AC16 Series Data Sheet, Rev. 8
BIT 6
BIT 1
2
...
...
...
BIT 2
BIT 5
6
BIT 1
BIT 6
7
BIT 0
BIT 7
8
Freescale Semiconductor
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