C8051F338-GM Silicon Laboratories Inc, C8051F338-GM Datasheet
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C8051F338-GM
Specifications of C8051F338-GM
Related parts for C8051F338-GM
C8051F338-GM Summary of contents
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Analog Peripherals - 10-Bit ADC (‘F336/8 only 200 ksps • external single-ended or differential inputs • VREF from on-chip VREF, external pin or V • Internal or external start of conversion source • Built-in temperature ...
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C8051F336/7/8/9 2 Rev. 1.0 ...
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Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 18 3. Pin Definitions.......................................................................................................... 19 4. QFN-20 Package Specifications ............................................................................. 23 5. QFN-24 Package Specifications ............................................................................. 25 6. Electrical Characteristics ........................................................................................ 27 6.1. Absolute Maximum Specifications..................................................................... 27 6.2. ...
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C8051F336/7/8/9 14. Special Function Registers................................................................................... 78 15. Interrupts ................................................................................................................ 82 15.1. MCU Interrupt Sources and Vectors................................................................ 83 15.1.1. Interrupt Priorities.................................................................................... 83 15.1.2. Interrupt Latency ..................................................................................... 83 15.2. Interrupt Register Descriptions ........................................................................ 84 15.3. External Interrupts /INT0 and /INT1................................................................. 89 16. ...
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Interfacing Port I Logic ............................................................. 121 20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 122 20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 122 20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 122 20.2.3. ...
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C8051F336/7/8/9 23.4. SPI0 Interrupt Sources .................................................................................. 171 23.5. Serial Clock Phase and Polarity .................................................................... 171 23.6. SPI Special Function Registers ..................................................................... 173 24. Timers ................................................................................................................... 180 24.1. Timer 0 and Timer 1 ...................................................................................... 182 24.1.1. Mode 0: 13-bit Counter/Timer ............................................................... ...
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... List of Figures 1. System Overview Figure 1.1. C8051F336/7 Block Diagram ................................................................ 16 Figure 1.2. C8051F338/9 Block Diagram ................................................................ 17 2. Ordering Information 3. Pin Definitions Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 21 Figure 3.2. QFN-24 Pinout Diagram (Top View) ..................................................... 22 4. QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing .................................................................... 23 Figure 4 ...
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C8051F336/7/8/9 15. Interrupts 16. Flash Memory Figure 16.1. Security Byte Decoding ....................................................................... 93 17. Reset Sources Figure 17.1. Reset Sources ................................................................................... 100 Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 101 18. Power Management Modes 19. Oscillators and Clock ...
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Figure 23.11. SPI Slave Timing (CKPHA = 1) ....................................................... 178 24. Timers Figure 24.1. T0 Mode 0 Block Diagram ................................................................. 183 Figure 24.2. T0 Mode 2 Block Diagram ................................................................. 184 Figure 24.3. T0 Mode 3 Block Diagram ................................................................. 185 Figure ...
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C8051F336/7/8/9 List of Tables 1. System Overview 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 18 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F336/7/8/9 ................................................. 19 4. QFN-20 Package Specifications Table 4.1. QFN-20 Package Dimensions ................................................................ 23 ...
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Table 20.1. Port I/O Assignment for Analog Functions ......................................... 122 Table 20.2. Port I/O Assignment for Digital Functions ........................................... 122 Table 20.3. Port I/O Assignment for External Event Trigger Functions ................. 123 21. SMBus Table 21.1. SMBus Clock Source Selection ...
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C8051F336/7/8/9 List of Registers SFR Definition 7.1. ADC0CF: ADC0 Configuration ...................................................... 41 SFR Definition 7.2. ADC0H: ADC0 Data Word MSB .................................................... 42 SFR Definition 7.3. ADC0L: ADC0 Data Word LSB ...................................................... 42 SFR Definition 7.4. ADC0CN: ADC0 Control ................................................................ 43 ...
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SFR Definition 20.4. P0MAT: Port 0 Match Register .................................................. 130 SFR Definition 20.5. P1MASK: Port 1 Mask Register ................................................. 130 SFR Definition 20.6. P1MAT: Port 1 Match Register .................................................. 131 SFR Definition 20.7. P0: Port 0 ................................................................................... 132 SFR Definition ...
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C8051F336/7/8/9 SFR Definition 25.3. PCA0PWM: PCA PWM Configuration ....................................... 217 SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 218 SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 219 SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte ..................................... 219 SFR ...
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... Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals The C8051F336/7 are available in a 20- pin QFN package and the C8051F338/9 are available in a 24-pin QFN package. Both package options are lead-free and RoHS compliant. See tion ...
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C8051F336/7/8/9 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte ISP Flash Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 512 Byte XRAM Power Net VDD GND Precision 24.5 MHz Oscillator Low-Freq. Oscillator External XTAL1 Oscillator ...
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... Power Net VDD SYSCLK GND Precision 24.5 MHz Oscillator Low-Freq. Oscillator External XTAL1 Oscillator XTAL2 Circuit System Clock Configuration Figure 1.2. C8051F338/9 Block Diagram C8051F336/7/8/9 Port I/O Configuration Digital Peripherals UART Port 0 Drivers Timers Priority Crossbar PCA/ Decoder WDT SMBus SPI ...
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... C8051F336/7/8/9 2. Ordering Information Table 2.1. Product Selection Guide C8051F336- 768 Y C8051F337- 768 Y C8051F338- 768 Y C8051F339- 768 — — — — — — — — Y Rev.1 QFN-20 Y QFN- QFN-24 Y QFN-24 ...
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Pin Definitions Table 3.1. Pin Definitions for the C8051F336/7/8/9 Name Pin Pin ’F336/7 ’F338 GND 2 3 RST C2CK C2D 5 6 P0. VREF P0 IDA0 P0. ...
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C8051F336/7/8/9 Table 3.1. Pin Definitions for the C8051F336/7/8/9 (Continued) Name Pin Pin ’F336/7 ’F338 P1.7 6 ...
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P0.0 1 GND 2 VDD 3 /RST/C2CK 4 P2.0/C2D 5 Figure 3.1. QFN-20 Pinout Diagram (Top View) C8051F336/7/8/9 C8051F336/7 Top View GND (optional) Rev.1.0 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 21 ...
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... C8051F336/7/8/9 P0.1 1 P0.0 2 GND 3 VDD 4 /RST/C2CK 5 P2.4/C2D 6 Figure 3.2. QFN-24 Pinout Diagram (Top View) 22 C8051F338/9 Top View GND (optional) Rev.1.0 18 P1.0 17 P1.1 16 P1.2 15 P1.3 14 P1.4 13 P1.5 ...
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QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing Table 4.1. QFN-20 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.00 2.15 e 0.50 BSC. E 4.00 BSC. E2 2.00 ...
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C8051F336/7/8/9 Figure 4.2. QFN-20 Recommended PCB Land Pattern Table 4.2. QFN-20 PCB Land Pattern Dimesions Dimension Min C1 3.70 C2 3.70 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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QFN-24 Package Specifications Figure 5.1. QFN-24 Package Drawing Table 5.1. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.55 2.70 e 0.50 BSC. E 4.00 BSC. E2 2.55 ...
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C8051F336/7/8/9 Figure 5.2. QFN-24 Recommended PCB Land Pattern Table 5.2. QFN-24 PCB Land Pattern Dimesions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. ...
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Electrical Characteristics 6.1. Absolute Maximum Specifications Table 6.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum ...
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C8051F336/7/8/9 6.2. Electrical Characteristics Table 6.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Digital Supply Voltage Normal Operation Writing or Erasing Flash Memory Digital Supply RAM Data Retention Voltage SYSCLK (System ...
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Table 6.3. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Conditions Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O ...
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C8051F336/7/8/9 Table 6.4. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions RST Output Low Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR Threshold (V ) ...
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Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Conditions Oscillator Frequency IFCN = 11b Oscillator Supply Current 25 °C, V ...
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C8051F336/7/8/9 Table 6.8. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input, 1 ...
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Table 6.9. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameter Conditions Linearity Slope Slope Error* Offset Temp = 0 °C Offset Error* Temp = 0 °C Note: Represents one standard ...
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C8051F336/7/8/9 Table 6.11. IDAC Electrical Characteristics – +85 °C, = 3.0 V Full-scale output current set unless otherwise specified. DD Parameter Conditions Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Output Compliance Range ...
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Table 6.12. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Conditions Response Time CP0+ – CP0– = 100 mV Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV Response ...
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C8051F336/7/8/9 6.3. Typical Performance Curves VDD = 3.6V 12.0 10.0 8.0 6.0 4.0 2.0 0 Figure 6.1. Normal Mode Digital Supply Current vs. Frequency VDD = 3.6V 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 6.2. ...
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ADC (ADC0, C8051F336/8 only) The ADC0 on the C8051F336 200 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. The ADC is fully configurable under soft- ware control via Special Function Registers. The ...
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C8051F336/7/8/9 7.1. Output Code Formatting The ADC is in Single-ended mode when the negative input is connected to GND. The ADC will be in Differ- ential mode when the negative input is connected to any other option. The output code ...
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The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 ...
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C8051F336/7/8/9 7.2.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling ...
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SFR Definition 7.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] 2 AD0LJST 1:0 UNUSED C8051F336/7/8 AD0LJST R Function ADC0 SAR Conversion ...
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C8051F336/7/8/9 SFR Definition 7.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 are the sign extension ...
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SFR Definition 7.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ...
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C8051F336/7/8/9 7.3. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 7.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 7.8. ADC0LTL: ADC0 Less-Than Data Low Byte ...
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C8051F336/7/8/9 7.3.1. Window Detector In Single-Ended Mode Figure 7.4 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF ...
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Window Detector In Differential Mode Figure 7.6 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the measurable voltage between the input pins is between –VREF ...
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C8051F336/7/8/9 7.4. ADC0 Analog Multiplexer (C8051F336/8 only) ADC0 on the C8051F336/8 has two analog multiplexers, referred to collectively as AMUX0. AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive ...
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... C8051F336/7/8 AMX0P[4: Function P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Temp Sensor V DD P2.0 (C8051F338/9 Only) P2.1 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) no input selected Rev.1 ...
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... AMX0N[4: Function P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 V REF GND (ADC in Single-Ended Mode) P2.0 (C8051F338/9 Only) P2.1 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) no input selected Rev.1 R ...
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Temperature Sensor (C8051F336/8 only) An on-chip temperature sensor is included on the C8051F336/8 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the positive ADC mux channel ...
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C8051F336/7/8/9 9. 10-Bit Current Mode DAC (IDA0, C8051F336/8 only) The C8051F336/8 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maxi- mum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and ...
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Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule an ...
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C8051F336/7/8/9 SFR Definition 9.1. IDA0CN: IDA0 Control Bit 7 6 IDA0EN IDA0CM[2:0] Name R/W Type 0 1 Reset SFR Address = 0xB9 Bit Name 7 IDA0EN IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. 6:4 IDA0CM[2:0] IDA0 Update Source Select ...
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SFR Definition 9.2. IDA0H: IDA0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0x97 Bit Name 7:0 IDA0[9:2] IDA0 Data Word High-Order Bits. Upper 8 bits of the 10-bit IDA0 Data Word. SFR Definition ...
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C8051F336/7/8/9 10. Voltage Reference (C8051F336/8 only) The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the VREF pin, or the V (see Figure 10.1). The ...
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SFR Definition 10.1. REF0CN: Reference Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7:4 UNUSED Unused. Read = 0000b; Write = don’t care. 3 REFSL Voltage Reference Select. This bit selects ...
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C8051F336/7/8/9 11. Comparator0 C8051F336/7/8/9 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 11.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a ...
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trical specifications are given in Section “6. Electrical Characteristics” on page 27. The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 11.2). Selecting a ...
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C8051F336/7/8/9 The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Compar- ator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic ...
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SFR Definition 11.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output ...
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C8051F336/7/8/9 SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt ...
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Comparator Multiplexer C8051F336/7/8/9 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 11.3). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; the ...
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... Function P0.1 P0.3 P0.5 P0.7 P1.1 P1.3 P1.5 P1.7 P2.1 (C8051F338/9 Only) P2.3 (C8051F338/9 Only) None P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 (C8051F338/9 Only) P2.2 (C8051F338/9 Only) None Rev.1 CMX0P[3:0] R ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F336/7/8/9 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion ...
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Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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C8051F336/7/8/9 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A ...
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Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement ...
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C8051F336/7/8/9 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first ...
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CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to ...
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C8051F336/7/8/9 SFR Definition 12.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer ...
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SFR Definition 12.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted ...
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C8051F336/7/8/9 13. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Program Memory The CIP-51 core has program memory space. The C8051F336/7/8/9 implements this pro- gram memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3DFF. The ...
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C8051F336/7/8/9 space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. ...
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SFR Definition 13.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xAA Bit Name 7:1 UNUSED Unused. Read = 0000000b; Write = Don’t Care 0 PGSEL XRAM Page Select. The ...
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C8051F336/7/8/9 14. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F336/7/8/9's resources and peripher- als. The CIP-51 controller core duplicates the ...
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Table 14.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ADC0 Greater-Than ...
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C8051F336/7/8/9 Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description 0xB1 External Oscillator Control OSCXCN 0x80 Port 0 Latch P0 0xFE Port 0 Mask Configuration P0MASK 0xFD Port ...
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Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description 0xD1 Voltage Reference Control REF0CN 0xEF Reset Source Configuration/Status RSTSRC 0x99 UART0 Data Buffer SBUF0 0x98 UART0 Control SCON0 ...
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C8051F336/7/8/9 15. Interrupts The C8051F336/7/8/9 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of ...
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MCU Interrupt Sources and Vectors The C8051F336/7/8/9 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be gener- ated ...
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C8051F336/7/8/9 Table 15.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B Port ...
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SFR Definition 15.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. ...
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C8051F336/7/8/9 SFR Definition 15.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 UNUSED Unused. Read = 1, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface ...
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SFR Definition 15.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer ...
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C8051F336/7/8/9 SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of ...
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External Interrupts /INT0 and /INT1 The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active ...
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C8051F336/7/8/9 SFR Definition 15.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL /INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX ...
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C8051F336/7/8/9 16.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: 1. Disable interrupts (recommended). 2. Erase the 512-byte Flash page containing the target location, as described in 3. Set the PSWE bit (register PSCTL). 4. ...
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Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in ...
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C8051F336/7/8/9 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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C8051F336/7/8/9 areas. 11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash. 16.4.3. System Clock 12.If operating from ...
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SFR Definition 16.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F Bit Name 7:2 UNUSED Unused. Read = 000000b, Write = don’t care. 1 PSEE Program Store Erase Enable ...
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C8051F336/7/8/9 SFR Definition 16.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and key function for ...
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SFR Definition 16.3. FLSCL: Flash Scale Bit 7 6 FOSE Reserved Reserved Name R/W R/W Type 1 0 Reset SFR Address = 0xB6 Bit Name 7 FOSE Flash One-shot Enable This bit enables the Flash read one-shot (recommended). If the ...
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C8051F336/7/8/9 17. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. Upon entering this reset state, the following events occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined ...
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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...
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C8051F336/7/8/9 17.2. Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 17.2). When level above ...
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SFR Definition 17.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is also ...
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C8051F336/7/8/9 17.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...
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SFR Definition 17.2. RSTSRC: Reset Source Bit 7 6 FERROR C0RSEF Name R R Type 0 Varies Varies Reset SFR Address = 0xEF Bit Name Description 7 UNUSED Unused. 6 FERROR Flash Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable ...
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C8051F336/7/8/9 18. Power Management Modes The C8051F336/7/8/9 devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented ...
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Idle mode if the WDT was initially configured to allow this operation. This pro- vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi- nitely, waiting for an ...
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C8051F336/7/8/9 SFR Definition 18.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop ...
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Oscillators and Clock Selection C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla- tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, ...
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C8051F336/7/8/9 SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7:2 UNUSED Unused. Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock Source Select Bits. ...
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Programmable Internal High-Frequency (H-F) Oscillator All C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period caPara1n be adjusted via the OSCICL register as defined by SFR ...
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C8051F336/7/8/9 SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. ...
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Programmable Internal Low-Frequency (L-F) Oscillator All C8051F336/7/8/9 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock ...
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C8051F336/7/8/9 19.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...
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SFR Definition 19.5. OSCXCN: External Oscillator Control Bit 7 6 XTLVLD XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is ...
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C8051F336/7/8/9 19.4.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...
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Capacitor values depend on crystal specifications Figure 19.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 19.4.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be ...
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C8051F336/7/8/9 19.4.3. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 19.1, Option 3. The capacitor should be no greater than 100 pF; however for ...
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... Digital and analog resources are available through 17 (C8051F336/ (C8051F338/9) I/O pins. Port pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 20.4. Port pin P2.4 on the C8051F338/9 and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal (C2D) ...
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C8051F336/7/8/9 20.1. Port I/O Modes of Operation Port pins P0.0 - P2.3 use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. ...
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WEAKPUD (Weak Pull-Up Disable) PxMDOUT.x (1 for push-pull) (0 for open-drain) XBARE (Crossbar Enable) Px.x – Output Logic Value (Port Latch or Crossbar) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral Px.x – Input Logic Value (Reads 0 ...
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C8051F336/7/8/9 20.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins P0.0 - P2.3 can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog ...
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Assigning Port I/O Pins to External Event Trigger Functions External event trigger functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I/O pin. The ...
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C8051F336/7/8/9 20.3. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 20.4) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
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Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART ...
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C8051F336/7/8/9 20.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) ...
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SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP0AE Name R R Type 0 0 Reset SFR Address = 0xE1 Bit Name 7:6 UNUSED Unused. Read = 00b; Write = Don’t Care. 5 CP0AE Comparator0 Asynchronous ...
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C8051F336/7/8/9 SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except ...
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Port Match Port match functionality allows system events to be triggered by a logic value change P1. A soft- ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0 ...
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C8051F336/7/8/9 SFR Definition 20.4. P0MAT: Port 0 Match Register Bit 7 6 Name Type 1 1 Reset SFR Address = 0xFD Bit Name 7:0 P0MAT[7:0] Port 0 Match Value. Match comparison value used on Port 0 for bits in P0MASK ...
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SFR Definition 20.6. P1MAT: Port 1 Match Register Bit 7 6 Name Type 1 1 Reset SFR Address = 0xED Bit Name 7:0 P1MAT[7:0] Port 1 Match Value. Match comparison value used on Port 1 for bits in P1MASK which ...
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C8051F336/7/8/9 SFR Definition 20.7. P0: Port 0 Bit 7 6 Name Type 1 1 Reset SFR Address = 0x80; Bit Addressable Bit Name Description 7:0 P0[7:0] Port 0 Data. Sets the Port latch logic value or reads the Port pin ...
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SFR Definition 20.9. P0MDOUT: Port 0 Output Mode Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA4 Bit Name 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if the corresponding bit in register ...
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C8051F336/7/8/9 SFR Definition 20.11. P1: Port 1 Bit 7 6 Name Type 1 1 Reset SFR Address = 0x90; Bit Addressable Bit Name Description 7:0 P1[7:0] Port 1 Data. Sets the Port latch logic value or reads the Port pin ...
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SFR Definition 20.13. P1MDOUT: Port 1 Output Mode Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA5 Bit Name 7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively). These bits are ignored if the corresponding bit in register ...
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C8051F336/7/8/9 SFR Definition 20.15. P2: Port 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA0; Bit Addressable Bit Name Description 7:5 UNUSED Unused. 4:0 P2[4:0] Port 2 Data. Sets the Port latch logic value ...
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SFR Definition 20.17. P2MDOUT: Port 2 Output Mode Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA6 Bit Name 7:5 UNUSED Unused. Read = 000b; Write = Don’t Care 4:0 P2MDOUT[4:0] Output Configuration Bits for ...
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C8051F336/7/8/9 21. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with ...
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Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, ...
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C8051F336/7/8/9 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE ...
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When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and ...
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C8051F336/7/8/9 Table 21.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as ...
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SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min- imum setup and hold times for ...
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C8051F336/7/8/9 SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
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C8051F336/7/8/9 SFR Definition 21.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is ...
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Table 21.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed by an address byte is ...
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C8051F336/7/8/9 of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this case, either value are acceptable on the incoming slave address. Additionally, if the GC ...
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SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask Bit 7 6 Name Type 1 1 Reset SFR Address = 0xE7 Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address ...
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C8051F336/7/8/9 21.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F336/7/8/9 21.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus ...
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Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events ...
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C8051F336/7/8/9 21.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave ...
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Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A ...
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C8051F336/7/8/9 Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte ...
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Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A ...
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C8051F336/7/8/9 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “22.1. ...
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C8051F336/7/8/9 22.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3. Figure 22.3. UART Interconnect Diagram 22.2.1. 8-Bit UART ...
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C8051F336/7/8/9 22.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
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Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...
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C8051F336/7/8/9 SFR Definition 22.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: ...
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SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x99 Bit Name 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register ...
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C8051F336/7/8/9 Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: ...
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Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...
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C8051F336/7/8/9 23.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 23.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
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SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
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C8051F336/7/8/9 Master Device Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 23.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured ...
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NSSMD1 (SPI0CN. and NSSMD0 (SPI0CN. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of ...
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C8051F336/7/8/9 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 23.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire ...
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SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) 23.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system ...
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C8051F336/7/8/9 SFR Definition 23.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI ...
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SFR Definition 23.2. SPI0CN: SPI0 Control Bit 7 6 SPIF WCOL MODF Name R/W R/W Type 0 0 Reset SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware ...
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C8051F336/7/8/9 SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module ...
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SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
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C8051F336/7/8/9 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...
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Table 23.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing (See Figure 23.8 and Figure 23.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge to ...
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C8051F336/7/8/9 24. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...
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SFR Definition 24.1. CKCON: Clock Control Bit 7 6 T3MH T3ML T2MH Name R/W R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 T3MH Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer ...
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C8051F336/7/8/9 24.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used ...
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Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR /INT0 Figure 24.1. T0 Mode 0 Block Diagram 24.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The ...
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C8051F336/7/8/9 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the ...
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Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
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C8051F336/7/8/9 SFR Definition 24.2. TCON: Timer Control Bit 7 6 TF1 TR1 Name R/W R/W Type 0 0 Reset SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Set hardware when Timer 1 ...
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SFR Definition 24.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of ...
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C8051F336/7/8/9 SFR Definition 24.4. TL0: Timer 0 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer ...
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SFR Definition 24.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. ...
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C8051F336/7/8/9 24.2. Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines ...
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Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH ...
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C8051F336/7/8/9 24.2.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock ...
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SFR Definition 24.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the ...
Page 194
C8051F336/7/8/9 SFR Definition 24.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the ...
Page 195
SFR Definition 24.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the ...
Page 196
C8051F336/7/8/9 24.3. Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines ...
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Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH ...
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C8051F336/7/8/9 24.3.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock ...
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SFR Definition 24.13. TMR3CN: Timer 3 Control Bit 7 6 TF3H TF3L TF3LEN Name R/W R/W Type 0 0 Reset SFR Address = 0x91 Bit Name 7 TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the Timer ...
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C8051F336/7/8/9 SFR Definition 24.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x92 Bit Name 7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the ...